DSPIC30F4012 datasheet(40/238 Pages) MICROCHIP

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dsPIC30F4011/4012

DS70135G-page 40

4.2.3

MODULO ADDRESSING

APPLICABILITY

Modulo Addressing can be applied to the Effective

Address (EA) calculation associated with any W register.

It is important to realize that the address boundaries

check for addresses less than or greater than the upper

(for incrementing buffers) and lower (for decrementing

buffers) boundary addresses (not just equal to). Address

changes may, therefore, jump beyond boundaries and

still be adjusted correctly.

4.3

Bit-Reversed Addressing

Bit-Reversed Addressing is intended to simplify data

reordering for radix-2 FFT algorithms. It is supported by

the X AGU for data writes only.

The modifier, which may be a constant value or register

contents, is regarded as having its bit order reversed.

The address source and destination are kept in normal

order. Thus, the only operand requiring reversal is the

modifier.

4.3.1

BIT-REVERSED ADDRESSING

IMPLEMENTATION

Bit-Reversed Addressing is enabled when:

BWM (W register selection) in the MODCON reg-

ister is any value other than 15 (the stack can not

be accessed using Bit-Reversed Addressing)

and

The BREN bit is set in the XBREV register and

The addressing mode used is Register Indirect

with Pre-Increment or Post-Increment.

If the length of a bit-reversed buffer is M = 2N bytes,

then the last ’N’ bits of the data buffer start address

must be zeros.

XB<14:0> is the Bit-Reversed Addressing modifier, or

‘pivot point’, which is typically a constant. In the case of

an FFT computation, its value is equal to half of the FFT

data buffer size.

When enabled, Bit-Reversed Addressing is only

executed for Register Indirect with Pre-Increment or

Post-Increment Addressing mode and word-sized data

writes. It will not function for any other addressing

mode or for byte-sized data, and normal addresses will

be generated instead. When Bit-Reversed Addressing

is active, the W Address Pointer will always be added

to the address modifier (XB) and the offset associated

with the Register Indirect Addressing mode will be

ignored.

addition,

word-sized

data

requirement, the LSb of the EA is ignored (and always

clear).

If Bit-Reversed Addressing has already been enabled

by setting the BREN bit (XBREV<15>), then a write to

the XBREV register should not be immediately followed

by an indirect read operation using the W register that

has been designated as the Bit-Reversed Pointer.

FIGURE 4-2:

BIT-REVERSED ADDRESS EXAMPLE

Note:

The modulo corrected Effective Address

is written back to the register only when

Pre-Modify or Post-Modify Addressing

mode is used to compute the Effective

Address. When an address offset (e.g.,

[W7+W2]) is used, Modulo Addressing

correction is performed, but the contents

of the register remain unchanged.

Note:

All bit-reversed EA calculations assume

word-sized data (LSb of every EA is

always clear). The XB value is scaled

accordingly to generate compatible (byte)

addresses.

Note:

Modulo Addressing and Bit-Reversed

Addressing

should

not

enabled

together. In the event that the user

attempts

this,

Bit-Reversed

Addressing will assume priority when

active for the X WAGU, and X WAGU

Modulo Addressing will be disabled.

However,

Modulo

Addressing

will

continue to function in the X RAGU.

b3 b2 b1

b2 b3 b4

Bit Locations Swapped Left-to-Right

Around Center of Binary Value

Bit-Reversed Address

XB = 0x0008 for a 16-Word Bit-Reversed Buffer

b7 b6 b5 b1

b7 b6 b5 b4

b11 b10 b9 b8

b15 b14 b13 b12

Sequential Address

Pivot Point

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