DSPIC30F4012 datasheet(18/238 Pages) MICROCHIP

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dsPIC30F4011/4012

DS70135G-page 18

2.2

Programmer’s Model

The programmer’s model is shown in Figure 2-1 and

consists of 16x16-bit working registers (W0 through

W15), 2x40-bit accumulators (ACCA and ACCB),

STATUS register (SR), Data Table Page register

(TBLPAG), Program Space Visibility Page register

(PSVPAG), DO and REPEAT registers (DOSTART,

DOEND, DCOUNT and RCOUNT) and Program Coun-

ter (PC). The working registers can act as data,

address or offset registers. All registers are memory

mapped. W0 acts as the W register for file register

addressing.

Some of these registers have a shadow register asso-

ciated with each of them, as shown in Figure 2-1. The

shadow register is used as a temporary holding register

and can transfer its contents to or from its host register

upon the occurrence of an event. None of the shadow

registers are accessible directly. The following rules

apply for transfer of registers into and out of shadows.

• PUSH.S and POP.S

W0, W1, W2, W3, SR (DC, N, OV, Z and C bits

only) are transferred.

• DO instruction

DOSTART, DOEND, DCOUNT shadows are

pushed on loop start and popped on loop end.

When a byte operation is performed on a working

mapped working registers is that both the Least and

Most Significant Bytes can be manipulated through

byte wide data memory space accesses.

2.2.1

SOFTWARE STACK POINTER/

FRAME POINTER

The dsPIC Digital Signal Controllers contain a software

stack. W15 is the dedicated software Stack Pointer

(SP) and is automatically modified by exception pro-

cessing and subroutine calls and returns. However,

W15 can be referenced by any instruction in the same

manner as all other W registers. This simplifies the

reading, writing and manipulation of the Stack Pointer

(e.g., creating stack frames).

W15 is initialized to 0x0800 during a Reset. The user

may reprogram the SP during initialization to any

location within data space.

W14 has been dedicated as a Stack Frame Pointer as

defined by the LNK and ULNK instructions. However,

W14 can be referenced by any instruction in the same

manner as all other W registers.

2.2.2

STATUS REGISTER

The dsPIC DSC core has a 16-bit STATUS register (SR),

the Least Significant Byte of which is referred to as the

SR Low Byte (SRL) and the Most Significant Byte as the

SR High Byte (SRH). See Figure 2-1 for SR layout.

SRL contains all the DSP ALU operation Status flags

(including the Z bit), as well as the CPU Interrupt Prior-

ity Level Status bits, IPL<2:0>, and the Repeat Active

Status bit, RA. During exception processing, SRL is

concatenated with the MSB of the PC to form a

complete word value which is then stacked.

The upper byte of the SR register contains the DSP

Adder/Subtracter Status bits, the DO Loop Active bit

(DA) and the Digit Carry (DC) Status bit.

2.2.3

PROGRAM COUNTER

The Program Counter is 23 bits wide. Bit 0 is always

clear; therefore, the PC can address up to 4M

instruction words.

Note:

In order to protect against misaligned

stack accesses, W15<0> is always clear.

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