DSPIC30F4012 datasheet(92/238 Pages) MICROCHIP

92 / 238 page

dsPIC30F4011/4012

DS70135G-page 92

14.1

Quadrature Encoder Interface

Logic

A typical, incremental (a.k.a. optical) encoder has three

outputs: Phase A, Phase B and an index pulse. These

signals are useful and often required in position and

speed control of ACIM and SR motors.

The two channels, Phase A (QEA) and Phase B (QEB),

have a unique relationship. If Phase A leads Phase B,

then the direction (of the motor) is deemed positive or

forward. If Phase A lags Phase B, then the direction (of

the motor) is deemed negative or reverse.

A third channel, termed index pulse, occurs once per

revolution and is used as a reference to establish an

absolute position. The index pulse coincides with

Phase A and Phase B, both low.

14.2

16-bit Up/Down Position Counter

Mode

The 16-bit Up/Down Counter counts up or down on

every count pulse, which is generated by the difference

of the Phase A and Phase B input signals. The counter

acts as an integrator, whose count value is proportional

to position. The direction of the count is determined by

the UPDN signal which is generated by the Quadrature

Encoder Interface Logic.

14.2.1

POSITION COUNTER ERROR

CHECKING

Position counter error checking in the QEI is provided

for and indicated by the CNTERR bit (QEICON<15>).

The error checking only applies when the position

counter is configured for Reset on the Index Pulse

modes (QEIM<2:0> = 110 or 100). In these modes, the

contents of the POSCNT register are compared with

the values (0xFFFF or MAXCNT + 1, depending on

direction). If these values are detected, an error condi-

tion is generated by setting the CNTERR bit and a QEI

count error interrupt is generated. The QEI count error

interrupt can be disabled by setting the CEID bit

(DFLTCON<8>). The position counter continues to

count encoder edges after an error has been detected.

The POSCNT register continues to count up/down until

a natural rollover/underflow. No interrupt is generated

for the natural rollover/underflow event. The CNTERR

bit is a read/write bit and reset in software by the user.

14.2.2

POSITION COUNTER RESET

The Position Counter Reset Enable bit, POSRES (QEI-

CON<2>) controls whether the position counter is reset

when the index pulse is detected. This bit is only

applicable when QEIM<2:0> = 100 or 110.

If the POSRES bit is set to ‘1’, then the position counter

is reset when the index pulse is detected. If the

POSRES bit is set to ‘0’, then the position counter is not

reset when the index pulse is detected. The position

counter will continue counting up or down and will be

reset on the rollover or underflow condition.

When selecting the INDX signal to reset the position

counter (POSCNT), the user has to specify the states

on the QEA and QEB input pins. These states have to

be matched in order for a Reset to occur. These states

are selected by the IMV<1:0> bits (DFLTCON<10:9>).

The Index Match Value bits (IMV<1:0>) allow the user

to specify the state of the QEA and QEB input pins,

during an index pulse, when the POSCNT register is to

be reset.

In 4x Quadrature Count mode:

IMV1 = Required state of Phase B input signal for

match on index pulse

IMV0 = Required state of Phase A input signal for

match on index pulse

In 2x Quadrature Count mode:

IMV1 = Selects phase input signal for index state

match (0 = Phase A, 1 = Phase B)

IMV0 = Required state of the selected phase input

signal for match on index pulse

The interrupt is still generated on the detection of the

index pulse and not on the position counter overflow/

underflow.

14.2.3

COUNT DIRECTION STATUS

As mentioned in the previous section, the QEI logic

generates an UPDN signal, based upon the relation-

ship between Phase A and Phase B. In addition to the

output pin, the state of this internal UPDN signal is

supplied to an SFR bit, UPDN (QEICON<11>), as a

read-only bit.

Note:

QEI pins are multiplexed with analog

inputs. The user must insure that all QEI

associated pins are set as digital inputs in

the ADPCFG register.

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