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STM32F101RF Datasheet(PDF) 12 Page - STMicroelectronics |
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STM32F101RF Datasheet(HTML) 12 Page - STMicroelectronics |
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12 / 108 page  Description STM32F101xF, STM32F101xG 12/108 Doc ID 17143 Rev 2 Figure 1. STM32F101xF and STM32F101xG access line block diagram 1. TA = –40 °C to +85 °C (junction temperature up to 105 °C). 2. AF = alternate function on I/O port pin. PA[15:0] EXT.IT 112AF AHB2 WKUP Fmax: 36 MHz VSS I2C2 GP DMA1 TIM2 TIM3 XTAL32kHz Flash 512 Kbyte VDD Backup interface TIM4 64 bit RTC RC 8 MHz Cortex-M3 CPU Dbus USART2 SPI2 Backup reg I2C1 RX, TX, CTS, RTS, USART3 RC 40 kHz Standby IWDG @VBAT POR /PDR @VDDA VBAT =1.8 V to 3.6 V CK, as AF RX, TX, CTS, RTS, CK, as AF NVIC SPI1 interface @VDDA PVD Int AHB2 APB2 AWU SPI3 UART4 RX, TX as AF UART5 RX,TX as AF TIM5 PLL @VDDA FSMC DAC_OUT1 as AF DAC_OUT2 as AF SRAM 80 Kbyte GP DMA2 TIM6 TIM7 NJTRST JTDI JTCK/SWCLK JTMS/SWDIO JTDO as AF A[25:0] D[15:0] CLK NOE NWE NE[4:1] NBL[1:0] NWAIT NL as AF 7 channels 5 channels GPIO port A GPIO port B GPIO port C GPIO port D GPIO port E GPIO port F GPIO port G USART1 Temp. sensor 12-bit ADC IF PB[15:0] PC[15:0] PD[15:0] PE[15:0] PF[15:0] PG[15:0] ADC_IN[0:15] @ VDDA APB1 Trace controller Pbus Ibus System Reset & clock control PCLK1 PCLK2 HCLK FCLK Power Volt. reg. 3.3 V to 1.8 V Supply supervision @VDD POR Reset NRST VDDA VSSA OSC_IN OSC_OUT @VDD XTAL OSC 4-16 MHz OSC32_IN OSC32_OUT TAMPER-RTC/ ALARM/SECOND OUT 4 channels as AF 4 channels as AF 4 channels as AF 4 channels as AF MOSI, MISO SCK, NSS as AF MOSI, MISO SCK, NSS as AF SCL, SDA, SMBA as AF SCL, SDA, SMBA as AF WWDG ai15830 TRACECLK TRACED[0:3] as AS SW/JTAG TPIU ETM Trace/trig V REF+ V REF– V REF+ MOSI, MISO, SCK, NSS as AF RX, TX, CTS, RTS as AF 12bit DAC1 IF IF IF 12bit DAC 2 TIM9 TIM10 TIM11 2 channels as AF 1 channel as AF 1 channel as AF TIM12 TIM13 TIM14 2 channels as AF 1 channel as AF 1 channel as AF MPU Flash 512 Kbyte 64 bit |
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