M68HC08 datasheet(68/332 Pages) FREESCALE

68 / 332 page

FLASH Memory

Technical Data

MC68HC908JB16 — Rev. 1.1

FLASH Memory

Freescale Semiconductor

4.9.1 Variables

The ROM-resident routines use three variables: CTRLBYT, CPUSPD

and LADDR; and one data buffer. The minimum size of the data buffer

is one byte and the maximum size is 64 bytes.

CPUSPD must be set before calling the erase or programming routines,

and should be set to four times the value of the CPU internal bus speed

in MHz. For example: for CPU speed of 6MHz, CPUSPD should be set

to 24.

4.9.2 ERASE Routine

The ERASE routine erases the entire or a block of FLASH memory. The

routine does not check for a blank range before or after erase.

NOTE:

A block erase cannot be performed on the last block of FLASH memory

(user vector at $FFD0)–$FFFF).

Table 4-2. Summary of FLASH Routine Variables

Variable

Address

Description

CTRLBYT

$0088

Control byte for setting mass or block erase.

CPUSPD

$0089

Timing adjustment for different CPU speeds.

LADDR

$008A–$008B

Last FLASH address to be programmed.

DATABUF

$0100–$013F

Data buffer for programming and verifying.

Table 4-3. ERASE Routine

Routine

ERASE

Calling Address

$FC06

Stack Use

5 Bytes

Input

CPUSPD — CPU speed

HX —

Contains any address in the range to be

erased

CTRLBYT — Mass or block erase

Mass erase if bit 6 = 1

Block erase if bit 6 = 0

M68HC08 Datasheet(PDF) 68 Page - Freescale Semiconductor, Inc

M68HC08 Datasheet(HTML) 68 Page - Freescale Semiconductor, Inc

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL