AD9512BCPZ datasheet(36/48 Pages) AD

Part #	AD9512BCPZ

Description	1.2 GHz Clock Distribution IC, 1.6 GHz Inputs, Dividers, Delay Adjust, Five Outputs

PDF	48 Pages

Scroll/Zoom	100%

Manufacturer	AD [Analog Devices]

Direct Link	http://www.analog.com

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36 / 48 page

AD9512

Rev. A | Page 36 of 48

CSB

SCLK

SDIO

tHI

tLO

tCLK

tDS

tDH

BI N

BI N + 1

Figure 37. Serial Control Port Timing—Write

Table 16. Serial Control Port Timing

Parameter

Description

tDS

Setup time between data and rising edge of SCLK

tDH

Hold time between data and rising edge of SCLK

tCLK

Period of the clock

Setup time between CSB and SCLK

Hold time between CSB and SCLK

tHI

Minimum period that SCLK should be in a logic high state

tLO

Minimum period that SCLK should be in a logic low state

CSB

CSB TOGGLE INDICATES

CYCLE COMPLETE

16 INSTRUCTION BITS + 8 DATA BITS

COMMUNICATION CYCLE 1

COMMUNICATION CYCLE 2

TIMING DIAGRAM FOR TWO SUCCESSIVE COMMUNICATION CYCLES. NOTE THAT CSB MUST

BE TOGGLED HIGH AND THEN LOW AT THE COMPLETION OF A COMMUNICATION CYCLE.

tPWH

SCLK

SDIO

Figure 38. Use of CSB to Define Communication Cycles

AD9512BCPZ Datasheet(PDF) 36 Page - Analog Devices