AD9512BCPZ datasheet(37/48 Pages) AD

37 / 48 page

AD9512

Rev. A | Page 37 of 48

SUMMARY TABLE

Table 17. AD9512 Register Map

Addr

(Hex)

Parameter

Bit 7 (MSB)

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

(LSB)

Def.

Value

(Hex)

Notes

Serial

Control Port

Configuration

SDO Inactive

(Bidirectional

Mode)

LSB

First

Soft

Reset

Long

Instruction

Not Used

01 to

Not Used

FINE DELAY

ADJUST

Fine

Delays

Bypassed

Delay Bypass 4

Not Used

Bypass

Delay

Full-Scale 4

Not Used

Ramp Capacitor <5:3>

Ramp Current <2:0>

Max. Delay

Full-Scale

Delay Fine

Adjust 4

Not Used

5-Bit Fine Delay <5:1>

Not Used

Min. Delay

Value

37, 38,

39, 3A,

3B, 3C

Not Used

OUTPUTS

LVPECL OUT0

Not Used

Output Level

<3:2>

Power-Down

<1:0>

LVPECL OUT1

Not Used

Output Level

<3:2>

Power-Down

<1:0>

LVPECL OUT2

Not Used

Output Level

<3:2>

Power-Down

<1:0>

LVDS_CMOS

OUT 3

Not Used

CMOS

Inverted

Driver On

Logic

Select

Output Level

<2:1>

Output

Power

LVDS, ON

LVDS_CMOS

OUT 4

Not Used

CMOS

Inverted

Driver On

Logic

Select

Output Level

<2:1>

Output

Power

LVDS, ON

42, 43,

Not Used

CLK1 AND

CLK2

Input

Receivers

Clocks Select,

Power-Down

(PD) Options

Not Used

CLKs

Not Used

Not

Used

CLK2

CLK1

Select

CLK IN

All Clocks

ON, Select

CLK1

46, 47,

48, 49

Not Used

DIVIDERS

Divider 0

Low Cycles <7:4>

High Cycles <3:0>

Divide by 2

Divider 0

Bypass

Sync

Force

Start H/L

Phase Offset <3:0>

Phase = 0

Divider 1

Low Cycles <7:4>

High Cycles <3:0>

Divide by 4

Divider 1

Bypass

Sync

Force

Start H/L

Phase Offset <3:0>

Phase = 0

Divider 2

Low Cycles <7:4>

High Cycles <3:0>

Divide by 8

AD9512BCPZ Datasheet(PDF) 37 Page - Analog Devices

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