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DSPIC33FJ32GP302TH/SP Datasheet(PDF) 302 Page - Microchip Technology |
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DSPIC33FJ32GP302TH/SP Datasheet(HTML) 302 Page - Microchip Technology |
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302 / 403 page  dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04 DS70292D-page 302 Preliminary 2009 Microchip Technology Inc. WDTPOST<3:0> FWDT Watchdog Timer Postscaler bits 1111 = 1:32,768 1110 = 1:16,384 • • • 0001 = 1:2 0000 = 1:1 FPWRT<2:0> FPOR Power-on Reset Timer Value Select bits 111 = PWRT = 128 ms 110 = PWRT = 64 ms 101 = PWRT = 32 ms 100 = PWRT = 16 ms 011 = PWRT = 8 ms 010 = PWRT = 4 ms 001 = PWRT = 2 ms 000 = PWRT = Disabled ALTI2C FPOR Alternate I2C™ pins 1 = I2C mapped to SDA1/SCL1 pins 0 = I2C mapped to ASDA1/ASCL1 pins JTAGEN FICD JTAG Enable bit 1 = JTAG enabled 0 = JTAG disabled ICS<1:0> FICD ICD Communication Channel Select bits 11 = Communicate on PGEC1 and PGED1 10 = Communicate on PGEC2 and PGED2 01 = Communicate on PGEC3 and PGED3 00 = Reserved, do not use TABLE 27-2: dsPIC CONFIGURATION BITS DESCRIPTION (CONTINUED) Bit Field Register Description Note 1: This Configuration register is not available on dsPIC33FJ32GP302/304 devices. |
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