DSPIC33FJ32GP302THSLASHSP datasheet(305/403 Pages) MICROCHIP

305 / 403 page

 2009 Microchip Technology Inc.

Preliminary

DS70292D-page 305

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04

27.5

JTAG Interface

dsPIC33FJ32GP302/304,

dsPIC33FJ64GPX02/X04,

and dsPIC33FJ128GPX02/X04 devices implement a

JTAG interface, which supports boundary scan device

testing, as well as in-circuit programming. Detailed

information on this interface is provided in future

revisions of the document.

27.6

In-Circuit Serial Programming

The dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/

X04, and dsPIC33FJ128GPX02/X04 devices can be

serially programmed while in the end application circuit.

This is done with two lines for clock and data and three

other lines for power, ground and the programming

sequence. Serial programming allows customers to

manufacture boards with unprogrammed devices and

then program the digital signal controller just before

shipping the product. Serial programming also allows

the most recent firmware or a custom firmware to be

programmed. Refer to the “dsPIC33F/PIC24H Flash

Programming Specification” (DS70152) for details

about In-Circuit Serial Programming (ICSP).

Any of the three pairs of programming clock/data pins

can be used:

• PGEC1 and PGED1

• PGEC2 and PGED2

• PGEC3 and PGED3

27.7

In-Circuit Debugger

When MPLAB® ICD 2 is selected as a debugger, the in-

circuit debugging functionality is enabled. This function

allows simple debugging functions when used with

MPLAB IDE. Debugging functionality is controlled

through the PGECx (Emulation/Debug Clock) and

PGEDx (Emulation/Debug Data) pin functions.

Any of the three pairs of debugging clock/data pins can

be used:

• PGEC1 and PGED1

• PGEC2 and PGED2

• PGEC3 and PGED3

To use the in-circuit debugger function of the device,

the design must implement ICSP connections to

MCLR, VDD, VSS, PGC, PGD and the PGECx and

PGEDx pin pairs. In addition, when the feature is

enabled, some of the resources are not available for

general use. These resources include the first 80 bytes

of data RAM and two I/O pins.

27.8

Code Protection and

CodeGuard™ Security

The

dsPIC33FJ64GPX02/X04

and

dsPIC33FJ128GPX02/X04 devices offer advanced

implementation of CodeGuard Security that supports

BS, SS and GS while, the dsPIC33FJ32GP302/304

devices offer the intermediate level of CodeGuard

Security that supports only BS and GS. CodeGuard

Security enables multiple parties to securely share

resources (memory, interrupts and peripherals) on a

single chip. This feature helps protect individual

Intellectual Property in collaborative system designs.

When coupled with software encryption libraries,

CodeGuard Security can be used to securely update

Flash even when multiple IPs reside on the single chip.

The code protection features vary depending on the

actual dsPIC33F implemented. The following sections

provide an overview of these features.

Secure segment and RAM protection is implemented

the

dsPIC33FJ64GPX02/X04

and

dsPIC33FJ128GPX02/X04

devices.

The

dsPIC33FJ32GP302/304 devices

do not support

secure segment and RAM protection.

Note:

Refer to Section 24. “Programming and

Diagnostics”

(DS70207)

the

“dsPIC33F/PIC24H

Family

Reference

Manual” for further information on usage,

configuration and operation of the JTAG

interface.

Note:

Refer to Section 23. “CodeGuard™

Security” (DS70199) of the “dsPIC33F/

PIC24H Family Reference Manual” for

further

information

usage,

configuration and operation of CodeGuard

Security.

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