DSPIC33FJ32GP302THSLASHSP datasheet(303/403 Pages) MICROCHIP

303 / 403 page

 2009 Microchip Technology Inc.

Preliminary

DS70292D-page 303

dsPIC33FJ32GP302/304, dsPIC33FJ64GPX02/X04, AND dsPIC33FJ128GPX02/X04

27.2

On-Chip Voltage Regulator

All

the

dsPIC33FJ32GP302/304,

dsPIC33FJ64GPX02/X04, and dsPIC33FJ128GPX02/

X04 devices power their core digital logic at a nominal

2.5V. This can create a conflict for designs that are

required to operate at a higher typical voltage, such as

3.3V. To simplify system design, all devices in the

dsPIC33FJ32GP302/304,

dsPIC33FJ64GPX02/X04,

and dsPIC33FJ128GPX02/X04 family incorporate an

on-chip regulator that allows the device to run its core

logic from VDD.

The regulator provides power to the core from the other

VDD pins. When the regulator is enabled, a low-ESR

(less than 5 Ohms) capacitor (such as tantalum or

ceramic) must be connected to the VCAP/VDDCORE pin

(Figure 27-1). This helps to maintain the stability of the

regulator. The recommended value for the filter capac-

itor is provided in Table 30-13 located in Section 30.1

“DC Characteristics”.

On a POR

, it takes approximately 20 s for the on-chip

voltage regulator to generate an output voltage. During

this time, designated as TSTARTUP, code execution is

disabled. TSTARTUP is applied every time the device

resumes operation after any power-down.

FIGURE 27-1:

CONNECTIONS FOR THE

ON-CHIP VOLTAGE

REGULATOR(1)

27.3

BOR: Brown-out Reset

The Brown-out Reset (BOR) module is based on an

internal voltage reference circuit that monitors the reg-

ulated supply voltage VCAP/VDDCORE. The main pur-

pose of the BOR module is to generate a device Reset

when a brown-out condition occurs. Brown-out condi-

tions are generally caused by glitches on the AC mains

(for example, missing portions of the AC cycle wave-

form due to bad power transmission lines, or voltage

sags due to excessive current draw when a large

inductive load is turned on).

A BOR generates a Reset pulse, which resets the

device. The BOR selects the clock source, based on

the device Configuration bit values (FNOSC<2:0> and

POSCMD<1:0>).

If an oscillator mode is selected, the BOR activates the

Oscillator Start-up Timer (OST). The system clock is

held until OST expires. If the PLL is used, the clock is

held until the LOCK bit (OSCCON<5>) is ‘1’.

Concurrently, the PWRT time-out (TPWRT) is applied

before the internal Reset is released. If TPWRT = 0 and

a crystal oscillator is being used, then a nominal delay

of TFSCM = 100 is applied. The total delay in this case

is TFSCM.

The BOR Status bit (RCON<1>) is set to indicate that a

BOR has occurred. The BOR circuit continues to oper-

ate while in Sleep or Idle modes and resets the device

should VDD fall below the BOR threshold voltage.

Note:

It is important for the low-ESR capacitor to

be placed as close as possible to the

VCAP/VDDCORE pin.

Note 1:

These are typical operating voltages. Refer

to Section TABLE 30-13: “Internal Volt-

age Regulator Specifications” located in

Section 30.1 “DC Characteristics” for

the full operating ranges of VDD and VCAP/

VDDCORE.

It is important for the low-ESR capacitor to

be placed as close as possible to the

VCAP/VDDCORE pin.

VDD

VCAP/VDDCORE

VSS

dsPIC33F

CEFC

3.3V

DSPIC33FJ32GP302TH/SP Datasheet(PDF) 303 Page - Microchip Technology

DSPIC33FJ32GP302TH/SP Datasheet(HTML) 303 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL