DM163006 datasheet(47/320 Pages) MICROCHIP

47 / 320 page

 2001 Microchip Technology Inc.

Advance Information

DS39541A-page 47

PIC18C601/801

4.6

Instruction Flow/Pipelining

An “Instruction Cycle” consists of four Q cycles (Q1,

Q2, Q3 and Q4). The instruction fetch and execute are

pipelined, such that fetch takes one instruction cycle,

while decode and execute takes another instruction

cycle. However, due to the pipelining, each instruction

effectively executes in one cycle. If an instruction

causes the program counter to change (e.g., GOTO),

two cycles are required to complete the instruction

(Example 4-2).

A fetch cycle begins with the program counter (PC)

incrementing in Q1.

In the execution cycle, the fetched instruction is latched

into the “Instruction Register” (IR) in cycle Q1. This

instruction is then decoded and executed during the

Q2, Q3, and Q4 cycles. Data memory is read during Q2

(operand read) and written during Q4 (destination

write).

4.7

Instructions in Program Memory

The program memory is addressed in bytes. Instruc-

tions are stored as two bytes or four bytes in program

memory. The Least Significant Byte of an instruction

word is always stored in a program memory location

with an even address (LSB = ’0’). Figure 4-1 shows an

example of how instruction words are stored in the pro-

gram memory. To maintain alignment with instruction

boundaries, the PC increments in steps of 2 and the

LSB will always read ’0’ (see Section 4.4).

The CALL and GOTO instructions have an absolute pro-

gram memory address embedded into the instruction.

Since instructions are always stored on word bound-

aries, the data contained in the instruction is a word

address. The word address is written to PC<20:1>,

which accesses the desired byte address in program

memory. Instruction #2 in Figure 4-1 shows how the

instruction “GOTO

0x06

” is encoded in the program

memory. Program branch instructions that encode a

relative address offset operate in the same manner.

The offset value stored in a branch instruction repre-

sents the number of single word instructions by which

the PC will be offset. Section 20.0 provides further

details of the instruction set.

EXAMPLE 4-2:

INSTRUCTION PIPELINE FLOW

TABLE 4-1:

INSTRUCTIONS IN PROGRAM MEMORY

Instruction

Opcode

Memory

Address

—

——

000007h

MOVLW 055h

0E55h

55h

000008h

0Eh

000009h

GOTO 000006h

EF03h, F000h

03h

00000Ah

EFh

00000Bh

00h

00000Ch

F0h

00000Dh

MOVFF 123h, 456h

C123h, F456h

23h

00000Eh

C1h

00000Fh

56h

000010h

F4h

000011h

—

——

000012h

All instructions are single cycle, except for any program branches. These take two cycles, since the fetch instruction

is “flushed” from the pipeline, while the new instruction is being fetched and then executed.

TCY0TCY1TCY2TCY3TCY4TCY5

1. MOVLW 55h

Fetch 1

Execute 1

2. MOVWF PORTB

Fetch 2

Execute 2

3. BRA SUB_1

Fetch 3

Execute 3

4. BSF

PORTA, BIT3 (Forced NOP)

Fetch 4

Flush

5. Instruction @ address SUB_1

Fetch SUB_1 Execute SUB_1

DM163006 Datasheet(PDF) 47 Page - Microchip Technology

DM163006 Datasheet(HTML) 47 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL