DM163006 datasheet(62/320 Pages) MICROCHIP

62 / 320 page

PIC18C601/801

DS39541A-page 62

Advance Information

 2001 Microchip Technology Inc.

4.14

RCON Register

The Reset Control (RCON) register contains flag bits

that allow differentiation between the sources of a

device RESET. These flags include the TO, PD, POR

and RI bits. This register is readable and writable.

RCON REGISTER

Note:

It is recommended that the POR bit be set

after a Power-on Reset has been detected,

so that subsequent Power-on Resets may

be detected.

R/W-0

U-0

R/W-1

R/W-0

U-0

IPEN

—

POR

bit 7

bit 0

bit 7

IPEN: Interrupt Priority Enable bit

= Enable priority levels on interrupts

= Disable priority levels on interrupts (16CXXX compatibility mode)

bit 6

Reserved: Maintain as ‘0’

bit 5

Unimplemented: Read as '0'

bit 4

RI: RESET Instruction Flag bit

= The RESET instruction was not executed

= The RESET instruction was executed causing a device RESET

(must be set in software after RESET instruction was executed)

bit 3

TO: Watchdog Time-out Flag bit

= After power-up, CLRWDT instruction, or SLEEP instruction

= A WDT time-out occurred

bit 2

PD: Power-down Detection Flag bit

= After power-up or by the CLRWDT instruction

= By execution of the SLEEP instruction

bit 1

POR: Power-on Reset Status bit

= A Power-on Reset has not occurred

= A Power-on Reset occurred

(must be set in software after a Power-on Reset occurs)

bit 0

Reserved: Maintain as ‘0’

Legend:

R = Readable bit

W = Writable bit

U = Unimplemented bit, read as ‘0’

- n = Value at POR

’1’ = Bit is set

’0’ = Bit is cleared

x = Bit is unknown

= Reserved

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