07XSC200 datasheet(23/51 Pages) FREESCALE

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Analog Integrated Circuit Device Data



Freescale Semiconductor

07XSC200

4.2.7

Chip Select (CSB)

The CSB pin enables communication with the master microcontroller (MCU). When this pin is in a logic [0] state, the device is

capable of transferring information to, and receiving information from, the MCU. The 07XSC200 latches in data from the Input

Shift registers to the addressed registers on the rising edge of CSB. The device transfers status information from the power output

to the Shift register on the falling edge of CSB. The SO output driver is enabled when CSB is logic [0]. CSB should transition from

a logic [1] to a logic [0] state only when SCLK is a logic [0]. CSB has an active internal pull-up from VDD, IUP.

4.2.8

Serial Clock (SCLK)

The SCLK pin clocks the internal shift registers of the 07XSC200 device. The serial input (SI) pin accepts data into the input shift

register on the falling edge of the SCLK signal while the serial output (SO) pin shifts data information out of the SO line driver on

the rising edge of the SCLK signal. It is important the SCLK pin be in a logic low state whenever CSB makes any transition. For

this reason, it is recommended the SCLK pin be in a logic [0] whenever the device is not accessed (CSB logic [1] state). SCLK

has an active internal pull-down. When CSB is logic [1], signals at the SCLK and SI pins are ignored and SO is tri-stated (high-

impedance) (see Figure 10, page 26). SCLK input has an active internal pull-down, IDWN.

4.2.9

Serial Input (SI)

This is a serial interface (SI) command data input pin. Each SI bit is read on the falling edge of SCLK. A 16-bit stream of serial

data is required on the SI pin, starting with D15 (MSB) to D0 (LSB). The internal registers of the 07XSC200 are configured and

controlled using a 5-bit addressing scheme described in Table 9, page 36. Register addressing and configuration are described

in Tables 10, page 36. SI input has an active internal pull-down, IDWN.

4.2.10 Digital Drain Voltage (VDD)

This pin is an external voltage input pin used to supply power to the SPI circuit. In the event VDD is lost (VDD Failure), the device

goes to Fail-safe mode.

4.2.11 Ground (GND)

These pins are the ground for the device.

4.2.12 Positive Power Supply (VPWR)

This pin connects to the positive power supply and is the source of operational power for the device. The VPWR contact is the

backside surface mount tab of the package.

4.2.13 Serial Output (SO)

The SO data pin is a tri-stateable output from the shift register. The SO pin remains in a high impedance state until the CSB pin

is put into a logic [0] state. The SO data is capable of reporting the status of the output, the device configuration, the state of the

key inputs, etc. The SO pin changes state on the rising edge of SCLK and reads out on the falling edge of SCLK. SO reporting

descriptions are provided in Table 22, page 42.

4.2.14 High Side Outputs (HS0, HS1)

Protected 7.0 m

 high side power outputs to the load.

07XSC200 Datasheet(PDF) 23 Page - Freescale Semiconductor, Inc