AD5381BSTZ-5 datasheet(25/40 Pages) AD

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Data Sheet

AD5381

Rev. D | Page 25 of 40

HARDWARE FUNCTIONS

RESET FUNCTION

Bringing the RESET line low resets the contents of allinternal

registers to their power-onreset state. Reset is a negative edge-

sensitive input. The default corresponds to m at full-scale and

to c at zero scale. The contents of the DACregistersarecleared,

setting VOUT0 to VOUT39 to 0 V. This sequence takes 270 µs.

The falling edge of RESET initiates the resetprocess; BUSYgoes

low for the duration, returning high when RESET is complete.

While BUSYis low, all interfaces are disabledand allLDAC

pulses are ignored.WhenBUSYreturns high, the part resumes

normal operation and the status of the RESET pin is ignored

until the next falling edge is detected.

ASYNCHRONOUS CLEAR FUNCTION

Bringing the CLR line low clears the contents of the DAC

registers to the data contained in the user configurable CLR

tion can be used in system calibrationto load zero-scale and

full-scale to all channels. The execution time for a CLR is 35 µs.

BUSY AND LDAC FUNCTIONS

BUSY is a digital CMOS output thatindicates the status of the

AD5381. The value of x2, the internal data loaded to the DAC

data register, is calculated each time the user writes newdata to

the corresponding x1, c, or m registers. During the calculation

of x2, the BUSYoutput goeslow. While BUSYis low, the user

can continue writing new data to the x1, m, or c registers, but

no DAC outputupdatescan take place. The DACoutputsare

updated by taking the LDACinput low. If LDACgoes low while

BUSY is active, the LDACevent is stored and the DACoutputs

update immediatelyafterBUSYgoes high. The user may hold

the LDACinput permanently low, in which case the DAC

outputs update immediately after BUSYgoes high. BUSY

also goes low during power-on reset and when a falling edge is

detected on the RESET pin. During this time, allinterfaces are

disabled and any eventson LDACare ignored.

The AD5381 contains an extra featurewhereby a DAC register

is not updated unless its x2 register has been written to since

the last time LDACwas brought low. Normally, when LDAC

is brought low, the DAC registers arefilled with the contents

of the x2 registers. However, theAD5381 will only update the

DAC registerif the x2 data has changed, thereby removing

unnecessary digital crosstalk.

FIFO OPERATIONINPARALLEL MODE

The AD5381 contains a FIFO to optimize operation when

operating in parallel interface mode. The FIFO Enable (level

sensitive, active high)is used to enable the internal FIFO. When

connected to DVDD, the internal FIFO is enabled, allowing the

user to write to the device at full speed. FIFO is only available in

parallel interface mode. The status of the FIFO EN pin is sam-

pled on power-up,and aftera CLR or RESET, to determineif

the FIFO is enabled. In either serial or I2C interface modes,

FIFO EN should be tied low. Up to 128 successive instructions

can be written to the FIFO at maximum speedin parallel mode.

When the FIFO is full, any further writes to the device are

ignored. Figure 29 shows a comparison between FIFO mode

and non-FIFO mode in terms ofchannel update time. Figure 29

also outlines digital loading time.

NUMBER OF WRITES

WITHOUT FIFO

(CHANNEL UPDATE TIME)

WITH FIFO

(CHANNEL UPDATE TIME)

WITH FIFO

(DIGITAL LOADING TIME)

Figure 29. Channel Update Rate (FIFO vs. NON-FIFO)

POWER-ONRESET

The AD5381 contains a power-on reset generator and state

machine. The power-on reset resetsall registers to a predefined

state and configures the analog outputsas high impedance.The

BUSY pin goes low during the power-on reset sequencing, pre-

venting data writes to the device.

POWER-DOWN

The AD5381 contains a global power-down featurethat putsall

channels into a low power modeand reduces the analog power

consumption to 2 µA max and digital power consumption to

20 µA max. In power-down mode, the output amplifier can be

configured as a high impedance outputor can providea 100 kΩ

load to ground. The contents ofall internal registers are retained

in power-down mode. When exiting power-down,the settling

time of the amplifier will elapse beforethe outputs settleto their

correct values.

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