AD5381BSTZ-5 datasheet(28/40 Pages) AD

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AD5381

Data Sheet

Rev. D | Page 28 of 40

I2C SERIAL INTERFACE

The AD5381 features an I2C-compatible2-wire interface

consisting of a serial data line (SDA)and a serial clock line

(SCL). SDA and SCL facilitate communication between the

AD5381 and the master at ratesup to 400 kHz. Figure 6 shows

the 2-wire interface timing diagrams that incorporatethree

different modes of operation. In selecting the I2C operating

mode, first configure serial operating mode (SER/PAR = 1)

and then select I2C mode by configuring the SPI/I2C pin to a

Logic 1. The device is connected to the I2C bus as a slave device

(that is, no clock is generated by the AD5381). The AD5381 has

a 7-bit slave address 1010 1(AD1)(AD0). The 5 MSB are hard-

coded and the 2 LSB are determinedby the stateof the AD1

and AD0 pins. The facility to hardware configure AD1 and AD0

allows four of these devices to be configured on the bus.

I2C Data Transfer

One data bit is transferred during each SCL clockcycle. The

data on SDA must remain stable during the high period of the

SCL clock pulse. Changesin SDA while SCL is high are control

signals that configure START and STOP conditions. Both SDA

and SCL are pulled high by the external pull-up resistors when

the I2C bus is not busy.

START and STOP Conditions

A master device initiates communication by issuing a START

condition. A START condition is a high-to-low transition on

SDA with SCL high. A STOP condition is a low-to-high

transition on SDA while SCL is high. A START condition

from the mastersignals the beginning of a transmission to

the AD5381. The STOP condition frees the bus. If a repeated

START condition (Sr) is generatedinsteadof a STOP condition,

the bus remains active.

Repeated START Conditions

A repeated START (Sr)condition may indicate a change of data

direction on the bus. Sr can be used when the bus masteris

writing to several I2C devices and wants to maintain control of

the bus.

Acknowledge Bit (ACK)

The acknowledge bit (ACK)is the ninth bit attached to any

8-bit data-word. ACKis always generatedby the receiving

device. The AD5381 devices generatean ACK whenreceiving

an address or data by pulling SDA low during the ninth clock

period. Monitoring ACK allowsfor detection of unsuccess-

ful data transfers. An unsuccessful data transfer occurs if a

receiving device is busy or if a system fault has occurred.

In the event of an unsuccessful data transfer, the busmaster

should reattempt communication.

AD5381 Slave Addresses

A bus masterinitiates communication with a slave device by

issuing a START condition followed by the 7-bit slave address.

When idle, the AD5381 waits for a START condition followed

by its slave address. TheLSB of the addresswordis the Read/

Write (R/W) bit. The AD5381is a receive only device; when

communicating with the AD5381, R/W = 0. After receiving the

proper address 1010 1(AD1)(AD0), the AD5381 issues an ACK

by pulling SDA low for one clockcycle.

The AD5381 has four different user programmable addresses

determined by the AD1 and AD0 bits.

Write Operation

There are threespecificmodes in which data can be written to

the AD5381 DAC.

4-Byte Mode

When writing to the AD5381 DACs, the user must begin

with an address byte(R/W = 0)after which the DAC acknowl-

edges that it is prepared to receive databy pulling SDA low.

The address byteis followed by the pointer byte; this addresses

the specific channel in the DAC to be addressed andis also

acknowledged by the DAC. Twobytesof data are then written

to the DAC, as shown in Figure 31. A STOP condition follows.

This allows the user to update a single channel within the

AD5381 at any time and requires fourbytes of datato be

transferred fromthe master.

3-Byte Mode

In 3-byte mode,the user can update morethan one channel in a

write sequence without having to write the device addressbyte

each time. The device address byte is only required once;sub-

sequent channel updates requirethe pointer byteand the data

bytes. In 3-byte mode, the userbegins with an address byte

(R/W = 0), after which the DAC willacknowledge that it is pre-

pared to receive databy pulling SDA low. The addressbyteis

followed by the pointer byte. This addresses thespecificchannel

in the DAC to be addressed and is also acknowledged by the

DAC. This is then followed by the two databytes. REG1 and

REG0 determine the register to be updated.

If a STOP condition doesnot follow thedatabytes, another

channel can be updated by sending a newpointerbyte followed

by the data bytes. Thismode only requires threebytes tobe

sent to updateany channel oncethe device hasbeen initially

addressed, andreduces thesoftwareoverhead in updating the

AD5381 channels.A STOP condition atany timeexitsthis mode.

Figure 32 showsa typical configuration.

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