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FG484 Datasheet(PDF) 37 Page - Microsemi Corporation |
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FG484 Datasheet(HTML) 37 Page - Microsemi Corporation |
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37 / 162 page ![]() ProASIC3E Flash Family FPGAs Revision 13 2-23 Table 2-23 • Schmitt Trigger Input Hysteresis Hysteresis Voltage Value (typ.) for Schmitt Mode Input Buffers Input Buffer Configuration Hysteresis Value (typ.) 3.3 V LVTTL/LVCMOS/PCI/PCI-X (Schmitt trigger mode) 240 mV 2.5 V LVCMOS (Schmitt trigger mode) 140 mV 1.8 V LVCMOS (Schmitt trigger mode) 80 mV 1.5 V LVCMOS (Schmitt trigger mode) 60 mV Table 2-24 • I/O Input Rise Time, Fall Time, and Related I/O Reliability* Input Buffer Input Rise/Fall Time (min.) Input Rise/Fall Time (max.) Reliability LVTTL/LVCMOS (Schmitt trigger disabled) No requirement 10 ns * 20 years (110°C) LVTTL/LVCMOS (Schmitt trigger enabled) No requirement No requirement, but input noise voltage cannot exceed Schmitt hysteresis. 20 years (110°C) HSTL/SSTL/GTL No requirement 10 ns * 10 years (100°C) LVDS/B-LVDS/M-LVDS/ LVPECL No requirement 10 ns * 10 years (100°C) Note: *For clock signals and similar edge-generating signals, refer to the "ProASIC3/E SSO and Pin Placement Guidelines" chapter of the ProASIC3E FPGA Fabric User’s Guide. The maximum input rise/fall time is related to the noise induced into the input buffer trace. If the noise is low, then the rise time and fall time of input buffers can be increased beyond the maximum value. The longer the rise/fall times, the more susceptible the input signal is to the board noise. Microsemi recommends signal integrity evaluation/characterization of the system to ensure that there is no excessive noise coupling into input signals. |
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