FG484 datasheet(11/162 Pages) MICROSEMI

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ProASIC3E Flash Family FPGAs

Revision 13

1-5

SRAM and FIFO

ProASIC3E devices have embedded SRAM blocks along their north and south sides. Each variable-

aspect-ratio SRAM block is 4,608 bits in size. Available memory configurations are 256×18, 512×9,

1k×4, 2k×2, and 4k×1 bits. The individual blocks have independent read and write ports that can be

configured with different bit widths on each port. For example, data can be sent through a 4-bit port and

read as a single bitstream. The embedded SRAM blocks can be initialized via the device JTAG port

(ROM emulation mode) using the UJTAG macro.

In addition, every SRAM block has an embedded FIFO control unit. The control unit allows the SRAM

block to be configured as a synchronous FIFO without using additional core VersaTiles. The FIFO width

and depth are programmable. The FIFO also features programmable Almost Empty (AEMPTY) and

Almost Full (AFULL) flags in addition to the normal Empty and Full flags. The embedded FIFO control

unit contains the counters necessary for generation of the read and write address pointers. The

embedded SRAM/FIFO blocks can be cascaded to create larger configurations.

PLL and CCC

ProASIC3E devices provide designers with very flexible clock conditioning capabilities. Each member of

the ProASIC3E family contains six CCCs, each with an integrated PLL.

The six CCC blocks are located at the four corners and the centers of the east and west sides.

To maximize user I/Os, only the center east and west PLLs are available in devices using the PQ208

package. However, all six CCC blocks are still usable; the four corner CCCs allow simple clock delay

operations as well as clock spine access.

The inputs of the six CCC blocks are accessible from the FPGA core or from one of several inputs

located near the CCC that have dedicated connections to the CCC block.

The CCC block has these key features:

•

Wide input frequency range (fIN_CCC) = 1.5 MHz to 350 MHz

•

Output frequency range (fOUT_CCC) = 0.75 MHz to 350 MHz

•

Clock delay adjustment via programmable and fixed delays from –7.56 ns to +11.12 ns

•

2 programmable delay types for clock skew minimization

•

Clock frequency synthesis

Additional CCC specifications:

•

Internal phase shift = 0°, 90°, 180°, and 270°. Output phase shift depends on the output divider

configuration.

•

Output duty cycle = 50% ± 1.5% or better

•

Low output jitter: worst case < 2.5% × clock period peak-to-peak period jitter when single global

network used

•

Maximum acquisition time = 300 µs

•

Low power consumption of 5 mW

•

Exceptional tolerance to input period jitter— allowable input jitter is up to 1.5 ns

•

Four precise phases; maximum misalignment between adjacent phases of 40 ps × (350 MHz /

fOUT_CCC)

Global Clocking

ProASIC3E devices have extensive support for multiple clocking domains. In addition to the CCC and

PLL support described above, there is a comprehensive global clock distribution network.

Each VersaTile input and output port has access to nine VersaNets: six chip (main) and three quadrant

global networks. The VersaNets can be driven by the CCC or directly accessed from the core via

multiplexers (MUXes). The VersaNets can be used to distribute low-skew clock signals or for rapid

distribution of high fanout nets.

FG484 Datasheet(PDF) 11 Page - Microsemi Corporation

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