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FG484 Datasheet(PDF) 41 Page - Microsemi Corporation |
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FG484 Datasheet(HTML) 41 Page - Microsemi Corporation |
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41 / 162 page ![]() ProASIC3E Flash Family FPGAs Revision 13 2-27 Timing Characteristics Table 2-31 • 3.3 V LVCMOS Wide Range High Slew Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 2.7 V Drive Strength Equivalent Software Default Drive Strength Option1 Speed Grade tDOUT tDP tDIN tPY tPYS tEOUT tZL tZH tLZ tHZ tZLS tZHS Units 100 µA 4 mA Std. 0.66 12.19 0.04 1.83 2.38 0.43 12.19 10.17 4.16 4.00 15.58 13.57 ns –1 0.56 10.37 0.04 1.55 2.02 0.36 10.37 8.66 3.54 3.41 13.26 11.54 ns –2 0.49 9.10 0.03 1.36 1.78 0.32 9.10 7.60 3.11 2.99 11.64 10.13 ns 100 µA 8 mA Std. 0.66 7.85 0.04 1.83 2.38 0.43 7.85 6.29 4.71 4.97 11.24 9.68 ns –1 0.56 6.68 0.04 1.55 2.02 0.36 6.68 5.35 4.01 4.22 9.57 8.24 ns –2 0.49 5.86 0.03 1.36 1.78 0.32 5.86 4.70 3.52 3.71 8.40 7.23 ns 100 µA 12 mA Std. 0.66 5.67 0.04 1.83 2.38 0.43 5.67 4.36 5.06 5.59 9.07 7.75 ns –1 0.56 4.82 0.04 1.55 2.02 0.36 4.82 3.71 4.31 4.75 7.71 6.59 ns –2 0.49 4.24 0.03 1.36 1.78 0.32 4.24 3.25 3.78 4.17 6.77 5.79 ns 100 µA 16 mA Std. 0.66 5.35 0.04 1.83 2.38 0.43 5.35 3.96 5.15 5.76 8.75 7.35 ns –1 0.56 4.55 0.04 1.55 2.02 0.36 4.55 3.36 4.38 4.90 7.44 6.25 ns –2 0.49 4.00 0.03 1.36 1.78 0.32 4.00 2.95 3.85 4.30 6.53 5.49 ns 100 µA 24 mA Std. 0.66 4.96 0.04 1.83 2.38 0.43 4.96 3.27 5.23 6.38 8.35 6.67 ns –1 0.56 4.22 0.04 1.55 2.02 0.36 4.22 2.78 4.45 5.43 7.11 5.67 ns –2 0.49 3.70 0.03 1.36 1.78 0.32 3.70 2.44 3.91 4.76 6.24 4.98 ns Notes: 1. The minimum drive strength for any LVCMOS 3.3 V software configuration when run in wide range is ±100 µA. Drive strength displayed in the software is supported for normal range only. For a detailed I/V curve, refer to the IBIS models. 2. Software default selection highlighted in gray. 3. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values. |
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