FG484 datasheet(98/162 Pages) MICROSEMI

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Pin Descriptions and Packaging

3-2

Revision 13

insufficient. If a device is in a JTAG chain of interconnected boards, the board containing the device can

be powered down, provided both VJTAG and VCC to the part remain powered; otherwise, JTAG signals

will not be able to transition the device, even in bypass mode.

Microsemi recommends that VPUMP and VJTAG power supplies be kept separate with independent

filtering capacitors rather than supplying them from a common rail.

VPUMP

Programming Supply Voltage

For programming, VPUMP should be 3.3 V nominal. During normal device operation, VPUMP can be left

floating or can be tied (pulled up) to any voltage between 0 V and the VPUMP maximum. Programming

power supply voltage (VPUMP) range is listed in the datasheet.

When the VPUMP pin is tied to ground, it will shut off the charge pump circuitry, resulting in no sources of

oscillation from the charge pump circuitry.

For proper programming, 0.01 µF and 0.33 µF capacitors (both rated at 16 V) are to be connected in

parallel across VPUMP and GND, and positioned as close to the FPGA pins as possible.

Microsemi recommends that VPUMP and VJTAG power supplies be kept separate with independent

filtering capacitors rather than supplying them from a common rail.

User-Defined Supply Pins

VREF

I/O Voltage Reference

Reference voltage for I/O minibanks. VREF pins are configured by the user from regular I/Os, and any

I/O in a bank, except JTAG I/Os, can be designated the voltage reference I/O. Only certain I/O standards

require a voltage reference—HSTL (I) and (II), SSTL2 (I) and (II), SSTL3 (I) and (II), and GTL/GTL+. One

VREF pin can support the number of I/Os available in its minibank.

User Pins

I/O

User Input/Output

The I/O pin functions as an input, output, tristate, or bidirectional buffer. Input and output signal levels are

compatible with the I/O standard selected.

During programming, I/Os become tristated and weakly pulled up to VCCI. With VCCI, VMV, and VCC

supplies continuously powered up, when the device transitions from programming to operating mode, the

I/Os are instantly configured to the desired user configuration.

Unused I/Os are configured as follows:

•

Output buffer is disabled (with tristate value of high impedance)

•

Input buffer is disabled (with tristate value of high impedance)

•

Weak pull-up is programmed

Globals

GL I/Os have access to certain clock conditioning circuitry (and the PLL) and/or have direct access to the

global network (spines). Additionally, the global I/Os can be used as regular I/Os, since they have

identical capabilities. Unused GL pins are configured as inputs with pull-up resistors.

See more detailed descriptions of global I/O connectivity in the "Clock Conditioning Circuits in Low Power

Flash Devices and Mixed Signal FPGAs" chapter of the ProASIC3E FPGA Fabric User’s Guide. All

inputs labeled GC/GF are direct inputs into the quadrant clocks. For example, if GAA0 is used for an

input, GAA1 and GAA2 are no longer available for input to the quadrant globals. All inputs labeled

GC/GF are direct inputs into the chip-level globals, and the rest are connected to the quadrant globals.

The inputs to the global network are multiplexed, and only one input can be used as a global input.

Refer to the I/O Structure section of the ProASIC3E FPGA Fabric User’s Guide for an explanation of the

naming of global pins.

FG484 Datasheet(PDF) 98 Page - Microsemi Corporation

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