AS3517H-ECTP datasheet(73/94 Pages) AMSCO

73 / 94 page

AS3517 V17

Data Sheet, Confidential

www.austriamicrosystems.com

Table 71 PMU PVDD1 Register

Name

Base

Default

PMU PVDD1

2-wire serial

00h

PVDD1 Low Drop-Out Regulator (LDO3) Control Register

Offset: 17h-1

This is an extended register and needs to be enabled by writing 001b to Reg. 18h first.

This register is reset at a DVDD-POR.

Bit

Bit Name

Default

Access

Bit Description

LDO_PVDD1_OFF

R/W

Power-down of LDO for PVDD1

0: PVDD1 (LDO3) enable

1: PVDD1 (LDO3) power-down

n/a

PROG_PVDD1

R/W

Enables settings either selected by external pins (VPRGx) or

settings stored in the 17h-1 register

0: VPRGx pins controlled

1: Register controlled

4:0

VSEL_PVDD1

00000

R/W

The voltage select bits set the LDO output in 2 different

resolution ranges

Range: 00h until 0Fh in 50mV steps

PVDD1=1.2V+VSEL_PVDD1*50mV

(1.2V until 1.95V)

Range: 10h until 1Fh in 100mV steps

PVDD1=2.0V+VSEL_PVDD1*100mV

(2.0V until 3.5V)

Table 72 PMU PVDD2 Register

Name

Base

Default

PMU PVDD2

2-wire serial

00h

PVDD2 Low Drop-Out Regulator (LDO4) Control Register

Offset: 17h-2

This is an extended register and needs to be enabled by writing 010b to Reg. 18h first.

This register is reset at a DVDD-POR.

Bit

Bit Name

Default

Access

Bit Description

LDO_PVDD2_OFF

R/W

Power-down of LDO for PVDD2

0: PVDD2 (LDO4) enable

1: PVDD2 (LDO4) power-down

n/a

PROG_PVDD2

R/W

Enables settings either selected by external pin (VPRGx) or

settings stored in the 17h-2 register

0: VPRGx pins controlled

1: Register controlled

4:0

VSEL_PVDD2

00000

R/W

The voltage select bits set the LDO output in 2 different

resolution ranges

Range: 00h until 0Fh in 50mV steps

PVDD2=1.2V+VSEL_PVDD1*50mV

(1.2V until 1.95V)

Range: 10h until 1Fh in 100mV steps

PVDD2=2.0V+VSEL_PVDD1*100mV

(2.0V until 3.5V)

Revision 1v3

- 93

AS3517H-ECTP Datasheet(PDF) 73 Page - ams AG

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