Electronic Components Datasheet Search
  English  ▼
ALLDATASHEET.NET

X  

AS3517H-ECTP Datasheet(PDF) 25 Page - ams AG

Part # AS3517H-ECTP
Description  Stereo Audio Codec with enhanced System Power Management
PDF  94 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  AMSCO [ams AG]
Direct Link  http://www.ams.com
Logo AMSCO - ams AG

AS3517H-ECTP Datasheet(HTML) 25 Page - ams AG

Back Button AS3517H-ECTP Datasheet HTML 21Page - ams AG AS3517H-ECTP Datasheet HTML 22Page - ams AG AS3517H-ECTP Datasheet HTML 23Page - ams AG AS3517H-ECTP Datasheet HTML 24Page - ams AG AS3517H-ECTP Datasheet HTML 25Page - ams AG AS3517H-ECTP Datasheet HTML 26Page - ams AG AS3517H-ECTP Datasheet HTML 27Page - ams AG AS3517H-ECTP Datasheet HTML 28Page - ams AG AS3517H-ECTP Datasheet HTML 29Page - ams AG Next Button
Zoom Inzoom in Zoom Outzoom out
 25 / 94 page
background image
AS3517 V17
Data Sheet, Confidential
© 2003-2007, austriamicrosystems AG, 8141 Unterpremstaetten, Austria-Europe. All Rights Reserved.
www.austriamicrosystems.com
via pin PWGD
Power Save Options
The bias current of the DAC block can be reduced in three steps down to 50% to reduce the power consumption.
Clock Supervision
The digital audio interface automatically checks the LRCLK. An interrupt can be generated when the state of the LRCLK input changes. A
bit in the interrupt register represents the actual state (present or not present) of the LRCLK.
Signal Description
The digital audio interface uses the standard I2S format:
•
left justified
•
MSB first
•
one additional leading bit
The first 18 bits are taken for DAC conversion. The on-chip synchronization circuit allows any bit-count up 32bit. When there are less than
18 bits sampled, the data sample is completed with “0”s. In I2S direct mode the data length has to be minimum 18 bits.
The ADC output is always 20 bit. If more SCLK pulses are provided, only the first 20 will be significant. All following bits will be “0”.
SCLK has not to be necessarily synchronous to LRCLK but the high going edge has to be separate from LRCLK edges. The LRCK signal
has to be derived from a jitter-free clock source, because the on-chip PLL is generating a clock for the digital filter, which has to be always
in correct phase lock condition to the external LRCLK.
Please observe that in slave mode LRCLK has to be activated before enabling the ADC.
In Master Mode operation SCLK has 32 clock cycles for each sample word.
64
*
4
256
*
4
LRCK
LRCLK
MCLK
SCLK
=
=
=
Sample Rates
In Master Mode AS3517 allows programming various sample rates. The master clock is generated by the 12-24MHz oscillator. Sampling
frequencies from 8kHz to 48kHz can be selected. For certain division ratios between master clock and sample ratio a certain deviation is
system inherent.
2
1
*
2
*
)
1
(
1
*
+
+
=
RD
PLLMode
f
LRCLK
OSC
)
511
0
(
.......
..........
)
2
,
1
(
......
......
..........
−
r
RateDivide
RD
factor
PLL
PLLMode
frequency
lator
Quarzoscil
f
osc
Revision 1v3
24
- 93



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com