AS3517H-ECTP datasheet(83/94 Pages) AMSCO

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AS3517 V17

Data Sheet, Confidential

www.austriamicrosystems.com

Table 86 First Interrupt Register

Name

Base

Default

IRQ_ENRD_0

2-wire serial

00h

First Interrupt Register

Offset: 23h

Please be aware that writing to this register will enable/disable the corresponding

interrupts, while with reading you get the actual interrupt status and will clear the

settings. This register is reset at a DVDD-POR.

Bit

Bit Name

Default

Access

Bit Description

CVDD2_EN_SD

Invokes shut-down of AFE when a –10% under-voltage spike at

CVDD2 occurs

0: disable

1: enable

CVDD2_UNDER

This bit is set when a –5% under-voltage at CVDD1 occurs

CVDD2_EN_IRQ

Enables interrupt for over-voltage/under-voltage supervision of

CVDD2

0: disable

1: enable

CVDD2_OVER

This bit is set when a +8% over-voltage at CVDD1 occurs

CVDD1_EN_SD

Invokes shut-down of AFE when a –10% under-voltage spike at

CVDD1 occurs

0: disable

1: enable

CVDD1_UNDER

This bit is set when a –5% under-voltage at CVDD1 occurs

CVDD1_EN_IRQ

Enables interrupt for over-voltage/under-voltage supervision of

CVDD1

0: disable

1: enable

CVDD1_OVER

This bit is set when a +8% over-voltage at CVDD1 occurs

PVDD2_EN_SD

Invokes shut-down of AFE when a –10% under-voltage spike at

PVDD2 occurs

0: disable

1: enable

PVDD2_UNDER

This bit is set when a –5% under-voltage at PVDD2 occurs

PVDD2_EN_IRQ

Enables interrupt for over-voltage/under-voltage supervision of

PVDD2

0: disable

1: enable

PVDD2_OVER

This bit is set when a +5% over-voltage at PVDD2 occurs

PVDD1_EN_SD

Invokes shut-down of AFE when a –10% under-voltage spike at

PVDD1 occurs

0: disable

1: enable

PVDD1_UNDER

This bit is set when a –5% under-voltage at PVDD1 occurs

PVDD1_EN_IRQ

Enables interrupt for over-voltage/under-voltage supervision of

PVDD1

0: disable

1: enable

PVDD1_OVER

This bit is set when a +5% over-voltage at PVDD1 occurs

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