Application Note

Sep 2008

9

Order Number: 320005-04

Conversion Guide: P33 130nm to 65nm

4.0

Hardware Design Considerations

The P33 130nm and P33 65nm flash memory devices provide reliable, two-bit-per-cell

storage technology for embedded applications. They satisfy the need for more density

in less space, with a high-speed interface. Both flash devices feature asymmetrically-

blocked architecture, Buffered Enhanced Factory Programming, and synchronous-burst

read mode. The following sections discuss hardware design considerations when

converting from the P33 130nm device to the P33 65nm device.

4.1

AC Read Specifications

Refer to the product datasheet for detailed list of all read timing specifications:

4.2

AC Write/Erase Specifications

Note:

Refer to the product datasheet for detailed list of all write and erase timing

specifications.

Table 3:

Key AC Read Specification Comparison

Features / Specifications

P33 130nm

P33 65nm

Performance

Clock Frequency (Max)

52 MHz

52 MHz

Easy BGA: 85 ns

Easy BGA: 95 ns

TSOP: 95 ns

TSOP: 105 ns

25 ns

25 ns

17 ns

17 ns

3ns

9 ns

9 ns

9 ns

9 ns

3.0 ns

5ns

Vcc power valid to RST# de-assertion (high)

60 us

300 us

Async Page Size

4 words

16 words

Synchronous Burst Length (word)

4-, 8-, 16-, and Cont.

4-, 8-, 16- and Cont.

Burst Suspend Mode

Yes

Yes