Application Note

Sep 2008

11

Order Number: 320005-04

Conversion Guide: P33 130nm to 65nm

5.0

Flash Software Design Considerations

The following sections discuss software design considerations when converting from the

P33 130nm device to the P33 65nm device.

5.1

Device Identification

The P33 130nm and P33 65nm flash devices have identical device identification codes.

5.2

Read Configuration Register (RCR)

Read configurations for both the P33 130nm and P33 65nm devices are configured

using the Read Configuration Register (RCR). For example, to place the device in

synchronous burst-read mode, you set the read mode bit in the RCR. The P33 65nm

RCR includes the following modifications to the RCR:

• Latency Count RCR[14:11]: an additional bit, RCR14, has been added to the P33

65nm device; RCR14 was reserved on P33 130nm. P33 65nm supports latency

counts of 8, 9, 10, 11, 12, 13, 14, and 15.

•WAIT Polarity RCR[10]: P33 130nm default setting high and P33 65nm default

setting is low.

• Data Hold RCR[9]: P33 130nm supports 1-clock or 2-clock cycle data hold. RCR[9] is

reserved for P33 65nm and supports a data hold of one cycle only.

•WAIT Delay RCR[8]: Same values for P33 130nm and P33-65nm.

• Burst Sequence RCR[7]: P33 130nm supports Linear “1” and Intel “0” burst order.

P33 65nm supports linear “0” only. Setting P33 65nm to “1” will not affect the burst

order; the burst order will always be linear.

• Clock Edge RCR[6]: Same values for P33 130nm and P33 65nm.

• Reserved RCR[5:4]: Same values for P33 130nm and P33 65nm.

•Burst Wrap RCR[3]: Same values for P33 130nm and P33 65nm.

• Burst Length RCR[2:0]: Same values for P33 130nm and P33 65nm.

Note:

The differences are summarized in the table below.

Table 6:

P33 Device ID Codes

Code Type

Address

Offset

Device

Density

P33-130nm Codes

P33-65nm Codes

Top

Bottom

Top

Bottom

Device Identification

0x01

256 Mbit

891F

8922

891F

8922