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CS4225 Datasheet(PDF) 6 Page - Cirrus Logic |
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CS4225 Datasheet(HTML) 6 Page - Cirrus Logic |
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6 / 30 page  SWITCHING CHARACTERISTICS - CONTROL PORT (TA = 25 oC VD+, VA+ = 5V±10%; Inputs: logic 0 = DGND, logic 1 = VD+, CL = 30pF) Parameter Symbol Min Max Units SPI Mode (H/S=0) CCLK Clock Frequency fsck 01 MHz CS High Time Between Transmissions tcsh 1.0 µs CS Falling to SCK Edge tcss 20 ns CCLK Low Time tscl 500 ns CCLK High Time tsch 500 ns CDIN to CCLK Rising Setup Time tdsu 250 ns CCLK Rising to DATA Hold Time CDIN (Note 9) tdh 50 ns CCLK Falling to CDOUT stable tpd 250 ns Rise Time of CDOUT tr1 25 ns Fall Time of CDOUT tf1 25 ns Rise Time of CCLK and CDIN tr2 100 ns Fall Time of CCLK and CDIN tf2 100 ns Notes: 9. Data must be held for sufficient time to bridge the transition time of CCLK. t r2 t f2 t dsu t dh t sch t scl CS CCLK CDIN t css t pd CDOUT t csh CS4225 6 DS86PP8 |
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