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CS4225 Datasheet(PDF) 5 Page - Cirrus Logic |
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CS4225 Datasheet(HTML) 5 Page - Cirrus Logic |
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5 / 30 page  SWITCHING CHARACTERISTICS (TA = 25°C; VA+, VD+ = +5V, outputs loaded with 30pF) Parameter Symbol Min Typ Max Units SCLK period tsckw 80 - - ns SCLK high time tsckh 25 - - ns SCLK low time tsckl 25 - - ns Input Transition Time 10% to 90% points - - 10 ns Input Clock Frequency Crystals 32 - 26000 kHz XTI 32 - 26000 kHz Input Clock (XTI) low time 30 - - ns Input Clock (XTI) high time 30 - - ns Input clock jitter tolerance - 500 - ps PLL clock recovery frequency LRCK, LRCKAUX 32 - 50 kHz SCLK, SCLKAUX 2.048 - 3.200 MHz CLKOUT duty cycle 45 50 55 % Audio ADC’s & DAC’s sample rate Fs 4 - 50 kHz RST-PDN low time (Note 5) 500 - - ns MSB output from LRCK edge (Format 1 and 3) tlrpd - - 50 ns SDOUT output from SCLK edge tdpd - - 50 ns SDIN setup time before SCLK edge tds - - 35 ns SDIN hold time after SCLK edge tdh - - 35 ns LRCK to SCLK delay (slave mode) tlrckd 35 - - ns LRCK to SCLK setup (slave mode) tlrcks 35 - - ns LRCK to SCLK alignment (master mode) tmslr -20 - 20 ns Note: 5. After Powering up the CS4225, RST-PDN should be held low for 50 ms to allow the voltage reference to settle. sckh sckl sckw t t t MSB MSB-1 *Active edge of SCLK, SCLKAUX depends on selected format. tdpd SDOUT1 SDOUT2 LRCKAUX (input) LRCK SCLK* SCLKAUX* (input) SDIN1 SDIN2 DATAUX dh t ds t lrpd t lrcks t lrckd t Audio Ports Slave Mode and Data I/O timing tmslr SCLK* SCLKAUX* (output) LRCK LRCKAUX (output) Audio Ports Master Mode Timing CS4225 DS86PP8 5 |
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