CS4225 datasheet(19/30 Pages) CIRRUS

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Reset

RST-PDN going low causes all the internal con-

trol registers, used in software mode, to be set to

the states indicated in Table 1. The reset states

are different for hardware mode, see the section

on Hardware Mode. RST-PDN must be brought

low and high at least once after power up. RST-

PDN returning high causes the CS4225 to

execute an offset calibration cycle. RST-PDN re-

turning high should occur at least 50ms after the

power supply has stabilized.

Power Down Mode

Placing the RST-PDN pin into a high impedance

state (floating) puts the CS4225 into the power

down mode. This may be done by driving the

RST-PDN pin with a three-state buffer, and set-

ting the buffer to the hi-z state. In power-down

mode CMOUT and VREF will not supply cur-

rent. If the master clock source stops, the

CS4225 will power down after 5

µs. Power down

will change all the control registers to the reset

state shown in Table 1.

After returning to normal operation from power

down, an offset calibration cycle must be exe-

cuted. To leave the power-down state, pull

RST-PDN low for at least 50ms to allow the in-

ternal voltage reference time to settle, then high

to initiate an offset calibration cycle.

De-Emphasis

Figure 8 shows the de-emphasis curve. De-em-

phasis may be enabled under hardware control,

using the DEM pin, or by software control using

the DEM bit. In software mode, either hardware

or software control of de-emphasis may be se-

lected.

The de-emphasis corner frequencies are as

shown in Figure 8 for a sample rate of 44.1kHz.

Selection of de-emphasis at other sample rates

will cause the filter to be applied, but with cor-

ner frequencies scaled proportionally to the

sample rate.

Hold Function (Software Mode only)

If the digital audio source has an invalid data

output pin, then the CS4225 may be configured

to cause the last valid analog output level to be

held constant. (This sounds much better than a

potentially random output level.) HOLD is sam-

pled on the active edge of SCLK. If HOLD is

driven high any time during the stereo sample

period, both pairs of DAC’s hold their current

output level, and reject the data currently being

input. SDIN input data is ignored while the

HOLD pin is high. For normal operation, the

HOLD pin must be low.

ATT6

→ ATT0

= 127

CS2, CS1,CS0 = 3

GN4

→ GN0

= 0

CI1, CI0

= 0

ADF1, ADF0

= 0

CO1, CO0

= 0

ACK1, ACK0

= 0

MUT4

→MUT1 = 1111

AMS

= 1

DEM

= 0

DDF2

→ DDF0

= 0

DEMC

= 0

DCK1, DCK1

= 0

MUTC

= 0

DMS

= 1

IS1, IS0

= 0

MAP

= 0

AIM

= 0

CAL

= 0

Table 1 - Reset State (Software Mode)

* with Fs = 44.1 kHz

Gain

-10dB

0dB

Frequency

T2 = 15us*

T1=50us*

(0.072 Fs)

(0.241 Fs)

Figure 8 - De-emphasis Curve.

CS4225

DS86PP8

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