DS2407 datasheet(25/31 Pages) DALLAS

25 / 31 page

DS2407

012099 25/31

READ/WRITE TIMING DIAGRAM Figure 15 (cont’d)

Write–zero Time Slot

VPULLUP

VPULLUP MIN

VIH MIN

VIL MAX

tSLOT

tREC

tLOW0

DS2407

SAMPLING WINDOW

µs

µs < tLOW0 < tSLOT < 120 µs

µs < tREC < 1

Read–data Time Slot

VPULLUP

VPULLUP MIN

VIH MIN

VIL MAX

tSLOT

tREC

tRDV

tLOWR

µs < tSLOT < 120 µs

µs < tLOWR < 15 µs

0 < tRELEASE < 45 µs

µs < tREC < 1

tRDV = 15 µs

tSU < 1 µs

tRELEASE

MASTER SAMPLING

WINDOW

RESISTOR

MASTER

DS2407

tSU

1–WIRE SIGNALING

The DS2407 requires strict protocols to insure data

integrity. The protocol consists of five types of signaling

on one line: Reset Sequence with Reset Pulse and

Presence Pulse, Write 0, Write 1, Read Data and Pro-

gram Pulse. All these signals except presence pulse are

initiated by the bus master. The initialization sequence

required to begin any communication with the DS2407

is shown in Figure 14. A reset pulse followed by a pres-

ence pulse indicates the DS2407 is ready to accept a

ROM command. The bus master transmits (TX) a reset

pulse (tRSTL, minimum 480 µs). The bus master then

releases the line and goes into receive mode (RX). The

1–Wire bus is pulled to a high state via the pull–up resis-

tor. After detecting the rising edge on the data pin, the

DS2407 waits (tPDH, 15–60 µs) and then transmits the

presence pulse (tPDL, 60–240 µs). If the device is pro-

grammed to power–up into the “Hidden Mode”, the

presence pulse will be observed only once during the

power–up phase. With every subsequent reset pulse no

presence pulse will be transmitted.

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