Product Specification

SP43503

Page 7 of 10

Table 11. Parallel and Direct Interface AC

Table 10. Serial Interface AC Characteristics

Figure 15. Serial Timing Diagram

Figure 16. Latched-Parallel/Direct-Parallel Timing Diagram

Symbol

Parameter

Min

Max

Unit

Serial clock frequency

-

10

MHz

Serial clock HIGH time

30

-

ns

Serial clock LOW time

30

-

ns

Last serial clock rising edge

setup time to Latch Enable

rising edge

10

-

ns

Latch Enable min. pulse width

30

-

ns

Serial data setup time

10

-

ns

Serial data hold time

10

-

ns

Parallel data setup time

100

-

ns

Parallel data hold time

100

-

ns

Address setup time

100

-

ns

Address hold time

100

-

ns

Parallel/Serial setup time

100

-

ns

Parallel/Serial hold time

100

-

ns

Digital register delay (internal)

-

10

ns

Symbol

Parameter

Min

Max

Unit

Latch Enable minimum

pulse width

30

-

ns

Parallel data setup time

100

-

ns

Parallel data hold time

100

-

ns

Parallel/Serial setup time

100

-

ns

Parallel/Serial hold time

100

-

ns

Digital register delay

(internal)

-

10

ns

Digital register delay

(internal, direct mode only)

-

5

ns

Characteristics

VALID

T

DISU

T

DIH

DI[6:2]

LE

P/S

T

PSSU

T

PSIH

T

LEPW

VALID

DO[6:2]

T

DIPD

T

PD

D[0], D[1] and D[7] must be set to logic low

Bits can either be set to logic high or logic low

D[0]

D[1]

D[2]

D[3]

D[4]

D[5]

D[7]

T

SISU

T

CLKL

T

LEPW

T

SIH

T

CLKH

SI

CLK

LE

P/S

T

LESU

T

PSSU

T

PSIH

VALID

T

DISU

T

PD

T

DIH

D[6]

DI[6:2]

DO[6:0]

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