PD488588FF datasheet(41/79 Pages) ELPIDA

41 / 79 page

Data Sheet

E0251N20 (Ver. 2.0)

µµµµPD488588FF-C80-40

Figure 22-1 Control Registers (2/7)

Control Register : CNFGB

Address : 02416

SVER5..0=ssssss

CORG4..0=01000

SPT0

DEVTYP2..0=000

BYTB

Read only register.

Field

Description

SVER5..0

Stepping version. Specifies the mask version number of this device.

CORG4..0

Core organization. This field specifies the number of bank (5 bits), row (9 bits), and column (7 bits) address bits.

SPT

Split-core. SPT=1 means the core is split, SPT=0 means it is not.

DEVTYP2..0

Device type. DEVTYP=000 means that this device is an RDRAM.

BYT

Byte width. B=1 means the device reads and writes 9-bit memory bytes.B=0 means 8 bits.

Control Register : TEST34

Address : 02216

Read/write register.

Reset values of TEST34 is zero (from SIO Reset).

This register are used for testing purposes. It must not be read or written after SIO Reset.

Control Register : DEVID

Address : 04016

DEVID4..0

Read/write register.

Reset value is undefined.

Field

Description

DEVID4..0

Device Identification register. DEVID4..DEVID0 is compared to DR4..DR0, DC4..DC0, and DX4..DX0 fields for all

memory read or write transactions. This determines which RDRAM is selected for the memory read or write

transaction.

PD488588FF Datasheet(PDF) 41 Page - Elpida Memory