82527 datasheet(19/22 Pages) INTEL

19 / 22 page

82527

3 Removed XTAL1 and XTAL2 from the excep-

tions for VIL spec XTAL1 VIL is now specified at

min eb05V max e 08V XTAL2 is an output

4 Removed XTAL1 and XTAL2 from the excep-

tions for VIH spec XTAL1 VIH is now specified at

min e 30V max e VCC a 05V XTAL2 is an

output

5 Source and Sink current for TX0 and TX1 were

corrected from minimum values to maximum val-

ues

6 Mode 2 The tAVSL specification was decreased

to 75 ns from 33 ns

7 Mode 2 The tSLAX specification was decreased

to 10 ns from 20 ns

8 Mode 3 Asynchronous The tDVCH specification

was decreased to 20 ns from 32 ns

9 All modes Two specifications were added for

CLKOUT

These

specifications

are

tCOPD

(CLKOUT Period) e (CDV a 1) tOSC and tCHCL

(CLKOUT High Period) e min (CDv a 1)

tOSC b 10 ns and max (CDV a 1)

tOSC a

15 ns NOTE CDV represented the value loaded

in the lower nibble of the CLKOUT Register

(1FH)

10 Serial Interface Mode The maximum SCLK (SPI

Clock) rate was increased to 8 MHz from 42

MHz The minimum tCYC (1SCLK) was set at

125 ns from 238 ns to reflect the increased max-

imum SPI clock rate

11 MODE01 the tWHQX Specifications was de-

creased to 10 ns from 125 ns

This is the -004 revision of the 82527 data sheet

The following differences exist between the -003

version and the -004 revision

1 Remove notice on page 1 concerning Advance

Information Data Sheet

2 Page 4 AS pin description add ‘‘pin tied high in

Asycnhronous mode 3’’

3 Page 4 E pin description add ‘‘pin tied high in

mode 3’’

4 Page 5 add VIH e 07 VCC and VIL e 03 VCC

for LSIO port pins (pins not used to interface to

host-CPU)

5 Page 6 change Differential Input Threshold

from MAX spec to MIN spec

6 Page 6 add Input Hysteresis spec for RX0RX1

0V maximum

7 Page 7 tLLAX decreased from 20 ns to 10 ns (to

interface to 20 MHz C196)

8 Page 7 tQVWH decreased from 30 ns to 27 ns

(to interface to 20 MHz C196)

9 Page 7 tWLWH decreased from 40 ns to 30 ns

(to interface to 20 MHz C196)

10 Page 7 tRLDV increased from 45 ns to 55 ns

11 Page 12 tCHKH specification added for VIH e

28V e 150 ns

12 Page 12 tCHAI decreased from 10 ns to 7 ns

13 Page 13 timing diagram for tAVCL revised to

show common CL low level

14 Page 14 tCHAI decreased from 10 ns to 7 ns

82527 Datasheet(PDF) 19 Page - Intel Corporation

82527 Datasheet(HTML) 19 Page - Intel Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22

Datasheet Download

Link URL