M80C196KB

ARCHITECTURE

The M80C196KB is a member of the MCS -96 family and as such has the same architecture and uses the

same instruction set as the M8096 Many new features have been added on the M80C196KB including

CPU FEATURES

Divide by 2 instead of divide by 3 clock for 15X performance

Faster instructions especially indexedindirect data operations

Faster interrupt response (almost twice as fast as 8096)

Powerdown and Idle Modes

6 new instructions including Compare Long and Block Move

8 new interrupt vectors6 new interrupt sources

PERIPHERAL FEATURES

SFR Window switching allows read-only registers to be written and vice-versa

Timer2 can count up or down by external selection

Timer2 has an independent capture register

HSO line events are stored in a register

HSO has CAM Lock and CAM Clear commands

New Baud Rate values are needed for serial port higher speeds possible in all modes

Double buffered serial port transmit register

Serial Port Receive Overrun and Framing Error Detection

PWM has a Divide-by-2 Prescaler

2