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M80C196KB Datasheet(PDF) 24 Page - Intel Corporation |
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M80C196KB Datasheet(HTML) 24 Page - Intel Corporation |
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24 / 30 page  M80C196KB AC Characteristics (Over Specified Operating Conditions) (Continued) Test Conditions Capacitive load on all pins e 100 pF Rise and fall times e 10 ns fOSC e 12 MHz The M80C196KB will meet these specifications Symbol Description Min Max Units Notes FXTAL Frequency on XTAL1 M80C196KB 35 12 MHz TOSC IFXTAL M80C196KB 83 286 ns TXHCH XTAL1 High to CLKOUT High or Low 20 110 ns TCLCL CLKOUT Cycle Time 2TOSC ns TCHCL CLKOUT High Period TOSC b 10 TOSCa10 ns TCLLH CLKOUT Falling Edge to ALE Rising b 10 10 ns TLLCH ALE Falling Edge to CLKOUT Rising b 15 15 ns TLHLH ALE Cycle Time 4TOSC ns TLHLL ALE High Period TOSC b 12 TOSCa12 ns TAVLL Address Setup to ALE Falling Edge TOSC b 20 ns TLLAX Address Hold after ALE Falling Edge TOSC b 40 ns TLLRL ALE Falling Edge to RD Falling Edge TOSC b 40 ns TRLCL RD Low to CLKOUT Falling Edge 4 25 ns TRLRH RD Low Period TOSCb5ns TRHLH RD Rising Edge to ALE Rising Edge TOSC TOSC a 25 ns (Note 2) TRLAZ RD Low to Address Float 10 ns TLLWL ALE Falling Edge to WR Falling Edge TOSC b 10 ns TCLWL CLKOUT Low to WR Falling Edge 0 25 ns TQVWH Data Stable to WR Rising Edge M80C196KB TOSC b 23 ns TCHWH CLKOUT High to WR Rising Edge b 515 ns TWLWH WR Low Period TOSC b 30 ns TWHQX Data Hold after WR Rising Edge TOSC b 15 ns TWHLH WR Rising Edge to ALE Rising Edge TOSC b 15 TOSC a 10 ns (Note 2) TWHBX BHE INST HOLD after WR Rising Edge TOSC b 15 ns NOTE 2 Assuming back-to-back bus cycles 24 |
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