AN1336 datasheet(7/10 Pages) STMICROELECTRONICS

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AN1336

Hysteresis

Hysteresis may be added to PFI for additional noise margin if desired (see Figure 7:

"Adding hysteresis"). The ratio of R1 and R2 should be selected such that PFI sees VPFI

when VUNREG falls to its trip point (VTRIP). Connecting R3 between PFI and PFO provides

the hysteresis and should typically be more than 10 times the value of R1 or R2. The

hysteresis window will extend both above (VH) and below (VL) the original trip point.

Figure 7: Adding hysteresis

Connecting an ordinary signal diode in series with R3 (see Figure 8: " Hysteresis on rising

VIN") so the lower trip point (VL) coincides with the trip point without hysteresis, causing the

entire hysteresis window to occur above VTRIP. This method provides additional noise

margin without compromising the accuracy of the power-fail threshold when the monitored

voltage is falling. The current through R1 and R2 should be at least 1 μA to ensure that the

25 nA PFI input current does not shift the trip point. The capacitor C1 is added for noise

rejection and should be quite small (e.g. ~100 nF), but is optional.

DocID007594 Rev 2

7/10

AI03077

PFO

VCC

PFI

VIN

GND

CONTROLLER

VIN

PFO

VTRIP

VTRIP = VPFI

(

)

R1 + R2

VH =

(

)

1 + 1 + 1

VPFI + VPFH

(

) R1

(

)

VL = R1

(

)

1 + 1 + 1

VPFI

[

]

VCC

–

where

VPFH = 10mV

VPFI = 1.25V

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