AN1336 datasheet(4/10 Pages) STMICROELECTRONICS

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PFI/PFO operation in a system (how does it

work?)

AN1336

PFI/PFO operation in a system (how does it work?)

Figure 5: PFI/PFO in a typical system

A typical power failure can be described by the following three events (see Figure 6:

"Power failure sequence"):

PFI triggered (t0): As VUNREG falls below the VPFI threshold, PFO is asserted on the

MCU’s Non-Maskable Interrupt (NMI) pin. When NMI is asserted, the MCU halts its

current task and begins saving critical data to the NVRAM (safeguard routine).

VCC begins to fall (t1): the MCU will continue functioning until the safeguard routine is

complete or RESET

occurs.

RESET

asserted and/or Write Protect occurs (t2):

At this point, the MCU needs to have completed the safeguard routine. This results in a

safeguard window from PFI to RESET /Write Protect (t2 - t0).

AC in

120/240V

50/60HZ

VPFI

MCU

SRAM

Regulator

VUNREG

VIN

VCC

VOUT

M41ST85W

PFI

PFO

NMI

INT

RST

INT

ECON

AI04220

4/10

DocID007594 Rev 2

AN1336 Datasheet(PDF) 4 Page - STMicroelectronics