AN4173 datasheet(6/22 Pages) STMICROELECTRONICS

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Considerations on the input impedance of the signal source

AN4173

6/22

Doc ID 023727 Rev 3

If this does not happen, that is, if the source resistance is mis-matched to the sample time, a

voltage loss will occur at the sample and hold stage. This voltage loss causes an accuracy

loss when increasing or decreasing the input voltage from 0 to VrefH.

The error is calculated by the formula:

Equation 1

where: tS = sample time in μs, R = RSOURCE +RL in Ω, C = CS in μF.

For example:

Since the error is proportional to the difference between VIN and VrefH, the effect produces a

non-linearity in the conversion of large-amplitude signals. In practice, if tS > 7RC, the

maximum error is reduced to less than half LSB (< 0.05%).

Figure 2.

Transient behavior during sampling phase

A possible workaround in order to avoid the distortion is compensate the high source

resistance adjusts the ADC’s sample rate. A slower sample rate can provide more time for

the ADC acquisition to overcome the distortion.

To minimize the error induced by voltage partitioning betweeen the equivalent resistance

REQ, (sampled voltage on CS +CP2) and the sum of RS and RF, the external circuit must be

designed to satisfy the following relation:

Equation 2

where REQ = 1/(fC × (CS+CP2)) and fC is the conversion rate.

Consider:

Maxerror

LSB

1024

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–

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

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LSB

AN4173 Datasheet(PDF) 6 Page - STMicroelectronics