Application code structure

AN4173

12/22

Doc ID 023727 Rev 3

3

Application code structure

This section gives an overview about the application code implemented to test the best

configuration, in terms of conversion time and conversion precision, for the input signal

used.

3.1

Peripherals used

●

Device: SPC564xB/C.

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System clock: 120 MHz by PLL initialization.

●

ADC frequency: 20 MHz.

●

PIT configuration: a trigger is arisen every 10 µs. This means a sample time of

100 kHz.

●

DMA and DMAMUX configuration: two channels used.

●

●

Sinusoidal signal at 10 kHz with an amplitude of 4.6 V and offset of 2.3 V.

3.2

Code implementation

The application configures the device to:

●

Disable the Software Watchdog

●

Configure modes and activate all clocks for all peripherals

●

Enable the Cache

●

Enable all exceptions and the ADC_EOC, PIT and STM interrupts

●

Set the GPIO in order to turn on some LEDs

●

●

Configure the PLL to work at 120 MHz.

●

Configure the ADC sample parameters setting, the sampling duration, the comparison

duration and the latching phase time. The ADC is set to One Shot Mode with DMA

feature enabled.

●

Configure the PIT to create a periodic interrupt every 10 µs for a sampling time of

100 kHz.

●

Initialize the DMA and DMAMUX :

–

Channel0: to move the ADC sampled values from the ADC ch0 to a buffer of 1024

elements, triggered by the EOC from DMAMUX channel 29

–

Channel1: to start the ADC acquisition from the ADC ch0, triggered by the PIT

with DMAMUX channel 60 (always enabled).

3.3

Performance comparisons

A brief performance comparison has been made using a constant value in order to measure

the conversion time of the ADC 10-bit on board.