ADC 10-bit timing configuration parameters

AN4173

10/22

Doc ID 023727 Rev 3

where

–INPSAMPLE

– ndelay = 0.5, if INPSAMPLE

2.3

Latency of the ADC conversion.

The Figure 3 shows the timing diagram in order to measure the time needed to complete

successfully an ADC conversion from the begin to the end of conversion, considering every

Tck needed for the sampling time (Tsample), for the evaluation time (Teval equal to 10 times

of Tck for 10 bits) and the delay of 0.5 or 1 Tck.

9

0.111

5

1

0

0.5

0.500

1.111

1.666

15

4.500

16

0.063

9

1

0

1

0.500

0.625

1.188

19

8.000

20

0.050

11

1

0

1

0.500

0.500

1.05

21

10.000

32

0.031

17

2

1

1

0.500

0.625

1.156

37

16.000

Table 1.

ADC sampling and conversion timing (continued)

Clock

(MHz)

TCK

(µs)

INPSAMP

IMPCMP

INPLATCH

ndelay

(µs)

(µs)

(µs)

TCK

TCK