ADC 10-bit timing configuration parameters

AN4173

8/22

Doc ID 023727 Rev 3

2

ADC 10-bit timing configuration parameters

In order to control the conversion time of the ADC_0 10-bit SAR peripheral, there are three

registers CTR0, CTR1, and CTR2.

The CTR0 register is associated with internal precision channels (from 0 to 15).

The CTR1 register is associated with internal standard channels (from 32 to 63).

The CTR2 register is associated with external multiplexed channels (from 64 to 95).

The three parameters involved in the evaluation of the conversion time are:

●

CTR.INPSAMP: used to configure the duration of the analog input signal sampling

operation. It represents the number of the clock cycles that this operation will last.

Minimum value is 3. If it is less, it is automatically set to 3 inside the ADC.

–

Range of values: [3:255]

●

CTR.INPLATCH: used to configure the duration of the latching phase during the 1-bit

evaluation of the SAR algorithm. 0 means half a clock cycle and 1 means one clock

cycle. The 1 condition is possible only if INPCMP is bigger than one. Otherwise it is

latch the comparator result. If 0, this time is equal to half the period of ADC clk. If 1, it is

equal to 1 TCK.

–

Range of values: [0:1]

●

CTR.INPCMP: used to configure the duration of the evaluation of each bit of the SAR

algorithm. It represents the number of clock cycles that this operation will last. Minimum

value is 1. If it is less, it is automatically set to 1 inside the ADC.

–

Range of values: [1:3]

ADC Clk: ADC peripheral input clock frequency from 6 to 32 MHz, depending on the

parameters and constraints.

2.1

Conversion timing

When a conversion is started, the ADC connects the internal sampling capacitor to the

respective analog input pin, allowing the capacitance to charge up to the input voltage

value. The time to load the capacitor is referred to as sampling time. After completion of the

sampling phase, the evaluation phase starts and all the bits corresponding to the resolution

of the ADC are estimated to provide the conversion result.

The conversion times are programmed via the bit fields of the CTR. Bit fields INPLATCH,

The sampling phase duration of ADC is given by:

Equation 5

where INPSAMPLE

T

sample

INPSAMPLE

ndelay

–

()

=

T

×

CK