General description

TN0897

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Doc ID 023176 Rev 2

1

General description

1.1

Feature list

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Standardized communication frame structure

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Variable frame width

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Global status information available in every communication frame

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In-frame response

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Pre-defined address assignment

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Fail-safe concept

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Robust communication protocol

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Bus fault detection

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Global failure Indication

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Product information

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Product name and family

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Silicon version

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Plug & play concept (standardized access to product information)

1.2

Signal description

Serial Clock (SCK): this input signal provides the timing of the serial interface. Data present

at Serial Data Input (SDI) is latched on the rising edge of Serial Clock (SCK). Data on Serial

Data Out (SDO) is shifted out at the falling edge of Serial Clock (SCK).

Serial Data Input (SDI): this input is used to transfer data serially into the device. It receives

the data to be written. Values are latched on the rising edge of Serial Clock (SCK).

Serial Data Output (SDO): this output signal is used to transfer data serially out of the

device. Data is shifted out on the falling edge of Serial Clock (SCK).

SDO also reflects the status of the <Global Error Flag> (Bit 7 of the <Global Status

Register>) while CSN is low and no clock signal is present

Chip Select Not (CSN): when this input signal is High, the device is not selected and Serial

Data Output (SDO) is high impedance. Driving this input Low enables the communication.

The communication must start and stop on a Low level of Serial Clock (SCK).

Failure Status (FSTAT) (optional): the <FSTAT> pin reflects the status of the <Global Error

Flag> (Bit 7 of the <Global Status Register>). It is an open-drain output signal so that

<FSTAT> pins of several devices can be connected to a common pull-up resistor and one

microcontroller I/O port in order to indicate a failure in the system.