TN0897

SPI communication flow

Doc ID 023176 Rev 2

11/28

Example 4

For 16-bit frames

Command Byte: 1111 1110

Data Byte: 0000 0000

Read register at ROM address 3EH (i. e. <SPI-frame-ID>)

2.3

Global status register

Table 3.

Global Status Register

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Global Error

Flag (GEF)

Comm Error

Not (Chip Reset

OR Comm Error)

TSD / chip

overload

prewarning

Device

specific

Device

specific

Fail

Safe

Table 4.

Definition of Global Status bits

Bit

Description

Optional

feature

Polarity

Comment

0

Fail Safe

X

Active high

The bit is defined as ‘0’ if no fail-safe functionality is

present in the device

1.

Fail-safe Mode is an operating mode where the device enters a safe state. The precise definition is device

specific and is defined in the product datasheet.

1

Device specific

X

2.

See Appendix A: Reference documents.

2

Device specific

X

Active high See product datasheet(2)

3

Temp pre-warning

X

Active high

The bit is defined as ‘0’ if feature is not present.

See product datasheet

4

Thermal

Shutdown / Chip

Overload

X

Active high

The bit is defined as ‘0’ if feature is not present.

See product datasheet

5

Not (Chip Reset

OR

Communication

Error)

Active low

Chip Reset: registers have been set to default

Communication Error: see bit 6

The bit is cleared automatically after a valid

communication with any register

After Power-On the bit is ‘0’ and is set to ‘1’ by a

valid SPI communication

6

Communication

Error

Active high

Bit is set if the number of clock cycles during

CSN = low does not match with the specified frame

width or if any other device specific communication

error occurs.

See product datasheet(2)

7

Global Error Flag

(GEF)

Active high

Logic OR combination of all failures in the <Global

Status register> and additional device specific

failures