Write operation

TN0897

18/28

Doc ID 023176 Rev 2

4.2

Format of data shifted out at SDO during write cycle

Figure 6.

SDO Frame composition during WRITE operation

Failures are indicated by activating the corresponding bit of the <Global Status> register.

The returned data byte(s) represent(s) the previous content of the accessed register.

Figure 7.

Write operation - 16 bit frame

Global status register

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

Global Error

Flag (GEF)

Comm

Error

Not (Chip Reset

OR Comm Error)

TSD / chip

overload

Device

specific

Device

specific

Fail

Safe

Data byte 1 - previous content of addressed register

MSB

LSB

D7

D6

D5

D4

D3

D2

D1

D0

1.

Only for 24-bit SPI frame width.

MSB

LSB

D7

D6

D5

D4

D3

D2

D1

D0

D0

D1

D2

D3

D4

D5

D6

D7

A0

A1

A2

A3

A4

A5

0

0

D0

D1

D2

D3

D4

D5

D6

D7

Fail

Safe

Dev

spec

Dev

spec

TSD /

Chip

OVL

NOT

(Chip

Res

OR

Comm

Err)

Com

Error

GEF

CSN

SDO

SDI

Command

Global Status

Data (8 bit)

Data

(previous content of

the register)

GAPGCFT00722