SPI communication flow

TN0897

8/28

Doc ID 023176 Rev 2

2

SPI communication flow

2.1

General description

The proposed SPI communication is based on a standard SPI interface structure using CSN

(Chip Select Not), SDI (Serial Data In), SDO (Serial Data Out/Error) and SCK (Serial Clock)

signal lines.

At device start-up the master reads the <SPI-frame-ID> register (ROM address 3EH) of the

slave device. This 8-bit register indicates the SPI frame length (16, 24, or 32 bit) and the

availability of additional features.

Each communication frame consists of an instruction byte which is followed by 1, 2 or 3 data

bytes.

The data returned on SDO within the same frame always starts with the <Global Status>

register. It provides general status information about the device. It is followed by 1, 2 or 3

data bytes (i. e. ‘In-frame-response’).

For write cycles the <Global Status> register is followed by the previous content of the

addressed register.

For read cycles the <Global Status> register is followed by the content of the addressed

register.