Card Clock

AN2269 - Application Note

6/25

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Card Clock

The card clock signal (CLK) is present on the CLK pin when the ST8024 is activated; it is

linked with the internal En4 signal (see

Figure 1 on page 1) and its frequency is obtained

according to the settings in

Table 1.

According to the ISO/IEC7816 specifications, the CLK duty cycle must be guaranteed

between 45% and 55%, even when the status of CLOCKDIV1 or CLOCKDIV2 changes.

Figure 4 shows how the ST8024 ensures duty cycle accuracy by waiting for completion of a

whole clock cycle before changing the frequency (CLKDIV1 change, rising edge of CH2).

The output Duty Cycle is 50%±5%, even if the Clock Division changes.

The card clock signal (CLK) can be obtained by connecting a crystal (“XTAL”) between the

XTAL1 and XTAL2 pins, or by an external signal applied to the XTAL1 pin. In this case the

XTAL2 pin must be left floating. The external signal voltage level must be limited between

Figure 4.

CLKDIV Change Clock Duty Cycle

Legend:

1.

CH1 = Output CLK Waveform

2.

CH2 = CLKDIV1 Pin

3.

4.

Mode: ACTIVE

5.

Table 1.

CLK Division Factor

CLKDIV1

CLKDIV2

0

0

01

1

1

10