February 2006

Rev 1

1/25

AN2269

Application Note

Using the ST8024 Smartcard Interface

Introduction

This application note provides information and suggestions for the optimal use and

performance of the ST8024 Smartcard Interface, including PCB layout, external component

placement, and connections (see

ST8024 Application Hardware Guidelines on page 16).

The ST8024 is a smart card interface designed to minimize microprocessor hardware and

software complexity in all applications that require a smart card (e.g., Set Top Box,

Electronic Payment, Pay TV, and Identification cards). It was developed in accordance with

New Digital Systems (NDS) conditional access requirements, and implements all of the

blocks and procedures for card activation/deactivation and checking (see

Figure 1).

Figure 1.

ST8024 Internal Block Diagram

21

6

7

5

4

8

17

14

16

15

10

9

13

12

11

PGND

VUP

VCC

CGND

RST

CLK

PRES

AUX1

Alarm

En1

En2

En3

En5

En4

En4

CLKUP

CLK

VREF

PVCC

AUX2

I/O

18

23

20

19

3

1

2

24

25

27

28

26

VDD

VDDP

S1

S2

PORADJ

RSTIN

CLKDIV1

Internal

Reference

Internal

Oscillator 2.5MHz

Voltage

Supervisor

Clock

Circuitry

Oscillator

Sequencer

Thermal

Protection

VCC

Generator

RST

Buffer

Clock

Buffer

I/O Transceiver

I/O Transceiver

I/O Transceiver

Supply

Step-up

Converter

ST8024

CLKDIV2

XTAL1

XTAL2

AUX1UC

AUX2UC

I/O UC

AI11884

22

GND

PRES

OFF

CMDVCC

5V/3V

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