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PD46185092B Datasheet(PDF) 25 Page - Renesas Technology Corp

Part # PD46185092B
Description  18M-BIT QDRTM II SRAM 2-WORD BURST OPERATION
PDF  36 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

PD46185092B Datasheet(HTML) 25 Page - Renesas Technology Corp

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μPD46185092B, μPD46185182B, μPD46185362B
R10DS0112EJ0200 Rev.2.00
Page 25 of 35
Nov 09, 2012
Scan Register Definition (1)
Register name
Description
Instruction register
The instruction register holds the instructions that are executed by the TAP controller
when it is moved into the run-test/idle or the various data register state. The register can
be loaded when it is placed between the TDI and TDO pins. The instruction register is
automatically preloaded with the IDCODE instruction at power-up whenever the controller
is placed in test-logic-reset state.
Bypass register
The bypass register is a single bit register that can be placed between TDI and TDO. It
allows serial test data to be passed through the RAMs TAP to another device in the scan
chain with as little delay as possible.
ID register
The ID Register is a 32 bit register that is loaded with a device and vendor specific 32 bit
code when the controller is put in capture-DR state with the IDCODE command loaded in
the instruction register. The register is then placed between the TDI and TDO pins when
the controller is moved into shift-DR state.
Boundary register
The boundary register, under the control of the TAP controller, is loaded with the contents
of the RAMs I/O ring when the controller is in capture-DR state and then is placed
between the TDI and TDO pins when the controller is moved to shift-DR state. Several
TAP instructions can be used to activate the boundary register.
The Scan Exit Order tables describe which device bump connects to each boundary
register location. The first column defines the bit’s position in the boundary register. The
second column is the name of the input or I/O at the bump and the third column is the
bump number.
Scan Register Definition (2)
Register name
Bit size
Unit
Instruction register
3
bit
Bypass register
1
bit
ID register
32
bit
Boundary register
107
bit
ID Register Definition
Part number
Organization
ID [31:28] vendor
revision no.
ID [27:12] part no.
ID [11:1] vendor
ID no.
ID [0] fix bit
μPD46185092B
2M x 9
XXXX
0000 0000 0101 0001
00000010000
1
μPD46185182B
1M x 18
XXXX
0000 0000 0000 1101
00000010000
1
μPD46185362B
512K x 36
XXXX
0000 0000 0000 1110
00000010000
1



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