AN2555 - Application note

Modified features

6/33

The three memory configurations possible for this 64 Kbytes of 'normal user data' are:

●

Default

The four DPP registers are assumed to contain their system startup value (0-3), providing one linear

data area of 64 Kbytes in the first segment (00’0000h - 00’FFFFh).

●

Addresses Linear

DPP3 contains page number 3, allowing access to ST10 registers and bit-addressable memory.

DPP0 - DPP2 provide a linear data area of 48 Kbytes anywhere in memory.

●

Paged

DPP3 contains page number 3, allowing access to ST10 registers and bit-addressable memory.

DPP0, DPP1 and DPP2 contain the page numbers of data areas of 16 Kbytes anywhere in memory.

The Default configuration can no longer be used. The other configurations offer the following possibilities:

●

with the Addresses Linear configuration the XRAM2 block is almost entirely covered with DPPs but

then accesses to constants must be made via EXTP instructions.

●

In the Paged configuration up to two DPPs can be assigned to XRAM2 and one DPP for constants.

1.3

Flash EEPROM

Table 3: Flash memory mapping shows the Flash memory address ranges of the 2 devices.

Table 2.

Flash memory key characteristics

ST10F269Zx

ST10F276Z5

Flash Size

256 Kbytes

832 KBytes

Flash Organization

7 blocks

4 banks, 17 blocks

Programming voltage

5 Volts

5 Volts

Programming method

Write/Erase Controller

Write/Erase Controller

Program/Erase cycles

100000 cycles

100000 cycles