AN2555 - Application note

New features

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2

New features

2.1

Additional XPeripherals

Some peripherals have been added to the ST10F276Z5. They are mapped on the X-Bus and are linked

to additional alternate functions of some ports of the ST10F276Z5.

The additional XPeripherals are the following:

●

A second SSC (SSC of ST10F269Zx becomes SSC0, while the new one is referred to as XSSC or

simply SSC1). Note that some restrictions and functional differences due to the XBUS peculiarities

are present between the standard SSC, and the new XSSC.

●

A second ASC (ASC0 of ST10F269Zx remains ASC0, while the new one is referred to as XASC or

simply as ASC1). Note that some restrictions and functional differences due to the XBUS

peculiarities are present between the standard ASC, and the new XASC.

●

A second PWM (PWM of ST10F269Zx becomes PWM0, while the new one is referred to as XPWM

or simply as PWM1). Note that some restrictions and functional differences due to the XBUS

peculiarities are present between the standard PWM, and the new XPWM.

●

An I²C interface is added (see X-I²C or simply I²C interface).

2.1.1

Hardware impacts

None if the additional XPeripherals are not used.

2.1.2

Software impacts

None if the additional Peripherals are not used. As they are XPeripherals, they can be enabled / disabled

via the XPERCON and SYSCON registers. By default, the settings of XPERCON and SYSCON are

compatible with the ST10F269Zx.

2.2

New multiplexer for X-Interrupts

The limited number of X-Bus interrupt lines of the present ST10 architecture, imposes some constraints

on the implementation of the new functionalities. In particular, the additional XPeripherals XSSC, XASC,

XI2C and XPWM need some resources to implement interrupts and PEC transfer. For this reason, a

complex but very flexible multiplexed structure for the interrupt is proposed. In Figure 2 the principle is

represented through a simple diagram, which shows the basic structure replicated for each of the four X-

interrupt vectors (XP0INT, XP1INT, XP2INT and XP3INT).

It is based on a new 16-bit register XIRxSEL (x=0,1,2,3), divided into two bytes:

●

Higher Byte (XIRxSEL[15:8]) Interrupt Enable bits

●

Lower Byte (XIRxSEL[7:0]) Interrupt Flag bits

When different sources submit an interrupt request, the enable bits (Higher Byte of XIRxSEL register)

define a mask which controls which sources will be associated with the unique available vector. If more

than one source is enabled to issue the request, the service routine has to identify the real event to be

serviced. This can easily be done by checking the flag bits (Lower Byte of XIRxSEL register). Note that

the flag bit can provide information about events which are not currently serviced by the interrupt

controller (since masked through the enable bits), allowing an effective software management also in the

absence of the possibility to serve the related interrupt request: a periodic polling of the flag bits may be

implemented inside the user application.