AN2555 - Application note

New registers

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4.3.2

Software impact

None. On the ST10F269Zx, the 00’E800h to 00’EBFFh address range was mapped onto external

memory but it was recommended to reserve this space for upward compatibility.

4.4

XMISC register

XREG

Reset Value: 0000h

4.4.1

Hardware impact

None.

4.4.2

Software impact

None.

On the ST10F269Zx, the CAN clock is the CPU clock but it is divided by 2 when calculating the time

quantum.

15 14 13 12 11 10

9

8

7

6

5

4

3

2

1

0

-

-

-

-

-

-

-

-

-

-

-

-

VREGOFF CANCK2 CANPAR ADCMUX

--

--

--

---

--

-

RW

RW

RW

RW

Bit

number

Bit name

Function

0

ADCMUX

Port1L ADC Channels Enable

‘0’: Analog inputs on port P5.y can be converted (default configuration)

‘1’: Analog inputs on port P1.z can be converted. Only 8 channels can be

managed

1CANPAR

CAN Parallel Mode Selection

‘0’: CAN2 is mapped on P4.4/P4.7, while CAN1 is mapped on P4.5/P4.6

‘1’: CAN1 and CAN2 are mapped in parallel on P4.5/P4.6. This is effective

only if both CAN1 and CAN2 are enabled by setting the CAN1EN and

CAN2EN bits in the XPERCON register. If CAN1 is disabled, CAN2 remains

on P4.4/P4.7 even if the CANPAR bit is set.

2

CANCK2

CAN Clock divider by 2 disable

‘0’: Clock provided to CAN modules is CPU clock divided by 2 (mandatory

‘1’: Clock provided to CAN modules is directly CPU clock

3VREGOFF

Main Voltage Regulator disable in Power-Down mode

‘0’: Default value after reset and when Power Down is not used

‘1’: Main Regulator is turned off when Power-Down mode is entered

4...15

Reserved