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UPD705102 Datasheet(PDF) 25 Page - NEC |
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UPD705102 Datasheet(HTML) 25 Page - NEC |
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25 / 80 page  µPD705102 25 Data Sheet U13675EJ2V1DS00 TM1 (16 bits) Clear & start TCLR1 Edge detection /2 /4 φ φ φ m m/4 m/16 φ φ m φ φ Note 1 Edge detection TI Note 2 INTOV1 Edge detection INTP10 Edge detection INTP11 Edge detection INTP12 Edge detection INTP13 CC10 CC11 CC12 CC13 S R Q Q TO10 INTCC10 INTCC11 S R Q Q TO11 INTCC12 INTCC13 Note 3 Note 3 The configurations of timer 1 and timer 4 are shown below. Figure 10-1. Block Configuration of Timer 1 Notes 1. Internal count clock 2. When the external count clock is TI: 6.0 MHz or lower: @input clock 6 × : 4.5 MHz or lower: @input clock 8 × 3. Reset priority Remarks 1. φ = bus clock: 48 M to 1.3 MHz: @input clock 6× : 36 M to 0.73 MHz: @input clock 8 × 2. φm = intermediate clock |
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